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1、1.0VerilogSynthesisMethodologyFinbarrO’Regan(finbarr@ee.ucd.ie)October2001Synthesisisacontraintdrivenprocessi.e.thesynthesisscriptneedstimingconstraintsFollowthefollowingmethodologyforbestresults1.Drawasimpleblockdiagram,labellingallsignals,widthsetc.2.Drawatimingdiagr
2、amwithasmuchdetailaspossible3.CodetheHDLaccordingtothesynthesizabletemplates4.Doaquick,loweffort,compile-justtoseeifitissynthesizablebeforesimulating.Comparethistotheblockdia-gram.Lookattheinferencereport:•countthenumberofflipflops-isitthesameasthenumberofflipflopsintheco
3、de.•checkforlatches-didyouwantthem.Ifnot,latchesareinferredincombinationalprocedures-theinferrencereporttellsyouwhichcombinationalprocedureandthenameofthelatch.Fullyspecifyallvariablesinallcasestoeliminatelatches.•Checkthecasestatementinferrence.Wasitfull/parallel?•Ch
4、eckanyincompleteeventlistwarnings?•Checktoseeifthereareanycombinationalfeedbackloops(typicallyonlyafteracompile).Combinationalfeed-backloopscanbeidentifiedbythesignalnamesinthetimingloop.•Checktheschematic-anyportsunconnected?•ChecktoseeifDesignwareandAmbitwarecomponen
5、tshavebeenbuiltcorrectly.Arethesethecomponentsthatyouwanted?Howmanydidyouwant?•Neverignoreanywarningthatthesynthesistoolflags.Allwarningsneedtobeunderstoodandtypicallysignedoff.5.Simulateandcomparewiththetimingdiagram•Ifyourdesigndoesn’tmeettimingbymorethan10%ofthecloc
6、kperiod,thengobacktothecode.Ifyouarewithin10%oftheclockperiod,thentryadifferentcompilestrategy.October18,200112.0SynthesizeableTemplates2.1CombinationalLogicacb//Usingareg//-----------------------------wirea,b;regc;always@(aorb)c=a&b;//Usingawire//--------------------
7、---------wirea,b,c;assignc=a&b;//usingabuiltinprimitive(withoutinstancename)//-----------------------------rega,b;wirec;and(c,a,b);//outputisalwaysfirstinthelist//usingabuiltinprimitive(withinstancename)//-----------------------------rega,b;wirec;andu1(c,a,b);//output
8、isalwaysfirstinthelist//ifcisanoutput//-----------------------------outputc;rega,b;assignc=a&b;October18,200122.2Multiplexer
