高速自校准CMOS片上时钟设计分析

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1、AbstractWiththehighdevelopmentofthedigitalsignalprocessingandthetelecommunica-tiontechnologies，AD／DAconventersarerequiredrapiddevelopmenttofollowthestepsoftheirsastheinterfacebetweenanaloganddigitalsignals．Recently,ADCstendtohavehigherspeedandhigherprecision,andtheclo

2、ckmoduleisdefinitelythekeytoguaranteethewholeperformance．Itismoreandmoreimportantforthedesignofhighspeedclockonchip．Nowadays，theclockgeneratorbasedonPLLissuchaproposalthatCanprovideavarietyoffrequencies、析廿llowercostandmoreefficiencyAfterthesummarizationofinternational

3、andnationalresearchdynamicstateonphase-lockedloopsandtheanlysisaboutPLLtheories，anewclockdesignusedinhigh-speedADCsisputfon忸rd

4、_——dlesignofhigh-speedself-calibrationCMOSclockonchip．Self-calibrationisthattheoutputclockisfeedbacktotheinputofdutycyclestabilizer(DCS)circu

5、it．Comparingwithotherclockgeneratordesigns，inthisdesign,theinputsignalisusedascontrolsignalinsteadofreferenceclocksignal晰the吨e·triggeredmode．Thewholearticleshowsthedesigncircuitsofeverymoduleandanlysisaboutthem．ThewholestuffissimulatedunderCadenceSpectrebasedonSMIC0．3

6、51maCMOSprocess．Fortheinputsignalat100M，dutycyclerangedfrom10％to90％callmeettherequirementofthe50％士5％regulationband．Thelockingtimeoftheloopislessthan500nsandthepeak-to-peakjitterislessthan13．5ps．ThiscircuitCanbetotallyappliedforhigh-speedADCs．Keyword：self-calibrationed

7、ge-triggeredDCSPLLhigh-speedADC1．．．．．．．．．．．．．．．．．．．．．．．．．．．．．一目录第一章绪论⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯．11．1课题的主要背景⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯．11．2锁相环的发展及国内外研究动态⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯21．2．1锁相环发展历史和基本分类⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯21．2．2国内外研究动态⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯31．3论文的内容安排⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯

8、⋯⋯⋯⋯⋯⋯⋯5第二章锁相环的基本原理⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯．72．1锁相环的构成⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯72．1．1锁相环的结构⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯．72．1．2锁相环的工作原理⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯．82．1．3锁相环路的稳定性参数⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯102．2电荷泵锁相环⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯。112．2．1鉴频／鉴相器的结构与动态分析⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯。112．2．2电荷泵的结构与

9、动态分析⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯132．2．3环路滤波器的结构与动态分析⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯142．2．4压控振荡器的数学模型⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯152．2．5分频器的数学模型⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯⋯