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1、42IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.43,NO.1,JANUARY2008AWidePowerSupplyRange,WideTuningRange,AllStaticCMOSAllDigitalPLLin65nmSOIJoséA.Tierno,AlexanderV.Rylyakov,Member,IEEE,andDanielJ.Friedman,Member,IEEEAbstract—AnallstaticCMOSADPLLfabricatedin65nmInthispaper,wedescribeaPLLreal
2、izationthatisdigital,digitalCMOSSOItechnologyhasafullyprogrammablepropor-thusavoidingtheissuesassociatedwithanalogPLLsintendedtional-integral-differential(PID)loopfilterandfeaturesathirdforuseinpredominantlydigitalchips.Becausethedigitalprop-orderdeltasigmamodulator.TheDCOisathreest
3、age,staticin-ertiesofthetechnologysunderlyingdevicestendtodegradeverterbasedringoscillatorprogrammablein768frequencysteps.TheADPLLlockrangeis500MHzto8GHzat1.3Vand25C,moregracefullywithreducedsupplyvoltagethandothecrit-and90MHzto1.2GHzat0.5Vand100C.TheICdissipatesicalanalogpropertie
4、s,thisPLLmayalsobewell-suitedtoap-8mW/GHzat1.2Vand1.6mW/GHzat0.5V.Thesynthesizedplicationsdemandingultra-lowsupplyvoltages.Keyelements4GHzclockhasaperiodjitterof0.7psrms,andlongtermjitterofthedesignincludeabang-bangphase/frequencydetector,theof6psrms.Thephasenoiseundernominaloperat
5、ingconditionsuseofunderflowsandoverflowsfromthefilterarithmeticunitsis112dBc/Hzmeasuredata10MHzoffsetfroma4GHzcenterfrequency.Thetotalcircuitareais200m150m.toenableacompactfilter/DCOcontrolimplementation,andaringoscillatorcomprisedofmultipledigitallycontrolledunits.IndexTerms—Bang-bang
6、phaseandfrequencydetectors,digitalphaselockedloops,phaselockedloops.Thepaperisorganizedasfollows.SectionIIdescribesthear-chitectureandschematic-leveldesignoftheDPLL.SectionIIIdescribesthephysicaldesignofthecircuit.InSectionIV,hard-I.INTRODUCTIONwaremeasurementsoftheDPLLoperatinginv
7、ariousmodesandsupplyvoltagedomainsarepresented.SectionVpresentsasummaryandconclusionsregardingthiswork.OMPLEXdigitalcircuitssuchasmicroprocessorstypi-Ccallyrequiresupportcircuitrythathastraditionallybeenrealizedusinganalogormixed-signalmacros.Acriticalex-II.ARCHITECTUREampleofsucha
8、supportcircuitisthephaselo