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1、476IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.39,NO.3,MARCH2004ANovelAll-DigitalPLLWithSoftwareAdaptiveFilterLimingXiu,SeniorMember,IEEE,WenLi,Member,IEEE,JasonMeiners,Member,IEEE,andRajithaPadakanti,Member,IEEEAbstract—Thephase-lockedloop(PLL)isoneofthekeybui
2、ldingblocksofmodernelectronicdesigns.ThispaperpresentsanovelPLLstructurethatutilizesa“flying-adder”frequencysynthesizerasitsdigitalcontroloscillator(DCO),asoftwareimplementedadaptiveIIRfilterasitsloopfilter,andauniquecounterasitsphasedetector.Thisall-dig
3、italPLL(ADPLL)achievedthedesiredfunctionalitywithadditionaladvantagesincludingnooff-chipRandCcomponentsrequired,dynamiccontroloftheloopgainonthefly,easyimplementationonthedigitalCMOSprocess.ThispaperpresentsdetaileddescriptionsofeachcomponentofthisADPLL;
4、italsopresentsthesystemmodelingin-domain,bymappingfrom-domain,fordynamicresponse,stability,andsteady-stateerrorstudy.IndexTerms—Adaptivefilter,flying-adder,frequencysynthe-Fig.1.Graphicdigitizersystem.sizer,phasedetector,phase-lockedloop.I.INTRODUCTIONOS
5、TpresentdigitalelectronicsystemsaredesignedMinsynchronousdesignstyle.Formixed-signaldesignswithanalogcomponents(ADC,DAC,etc.)onchip,theanalogcomponentsusuallyalsoworksynchronouslywithclockedge.ClockgenerationisoneofthemostimportantissuesinmodernVLSIdesig
6、nsandthephase-lockedloop(PLL)isthekeyelementinthispuzzle.Forexample,Fig.1istheblockdiagramofagraphicdigitizersystemthatconvertsanalogvideoFig.2.BlockdiagramoftheADPLL.waveformstodigitalsignalsforLCDmonitorsanddigitalTVapplications.Boththedigitalblocksand
7、theADCsoperateonisthesteady-stateerrorstudy.TherealADPLLimplementationvariousclocksgeneratedbytheon-chipPLL.isshowninSectionV.Inthissystem,thePLLneedstolocktothehorizontalsyn-chronization(HS)signalandgeneratethepixelclockfortheII.COMPONENTSOFTHEADPLLADCs
8、,andotherclocksforvariousdigitalfunctionblocks.ThisA.Second-OrderSystemPLLcanbeconstructedasaconventionalPLLwithananalogvoltage-controlledoscillator(VCO)andananalogloopfilter.Fig.2istheblockdiagramofthisADPLL.Asshown,itisA
