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1、顶层文件：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfreqtestisPORT(CLK:INSTD_LOGIC;Fsin:INSTD_LOGIC;DOUT0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);DOUT1:OUTSTD_LOGIC_VECTOR(7DOWNTO4);DOUT2:OUTSTD_LOGIC_VECTOR(11DOWNTO8);DOUT3:OUTSTD_LOGIC_VECTOR(15DOWNTO12);ou:OUTSTD_L
2、OGIC);endfreqtest;architecturestrucoffreqtestiscomponentTESTCTLPORT(CLKK:INSTD_LOGIC;CNT_EN,RST_CNT,LOAD:OUTSTD_LOGIC);ENDcomponent;componentcnt10PORT(en:instd_logic;rst:instd_logic;clk:instd_logic;cq:outstd_logic_vector(3downto0);cout:outstd_logic);ENDcomponent;componentREG4BPORT(LOAD:
3、INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDcomponent;signaltsten1,clr_cnt1,load1,CARRY_OUT0,CARRY_OUT1,CARRY_OUT2:std_logic;signalDIN:STD_LOGIC_VECTOR(15DOWNTO0);beginu1:TESTCTLportmap(CLKK=>CLK,CNT_EN=>tsten1,RST_CNT=>clr_cnt1,LOAD=>load1);u2:cn
4、t10portmap(en=>tsten1,clk=>Fsin,rst=>clr_cnt1,cq=>DIN(3DOWNTO0),cout=>carry_OUT0);U3:cnt10portmap(en=>tsten1,clk=>carry_OUT0,rst=>clr_cnt1,cq=>DIN(7DOWNTO4),cout=>carry_OUT1);U4:cnt10portmap(en=>tsten1,clk=>carry_OUT1,rst=>clr_cnt1,cq=>DIN(11DOWNTO8),cout=>carry_OUT2);U5:cnt10portmap(en
5、=>tsten1,clk=>carry_OUT2,rst=>clr_cnt1,cq=>DIN(15DOWNTO12),cout=>ou);U6:REG4Bportmap(LOAD=>load1,DIN=>DIN(3downto0),DOUT=>DOUT0(3downto0));U7:REG4Bportmap(LOAD=>load1,DIN=>DIN(7downto4),DOUT=>DOUT1(7downto4));U8:REG4Bportmap(LOAD=>load1,DIN=>DIN(11downto8),DOUT=>DOUT2(11downto8));U9:REG
6、4Bportmap(LOAD=>load1,DIN=>DIN(15downto12),DOUT=>DOUT3(15downto12));ENDstruc;测频器文件：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYTESTCTLISPORT(CLKK:INSTD_LOGIC;--1HZCNT_EN,RST_CNT,LOAD:OUTSTD_LOGIC);ENDTESTCTL;ARCHITECTUREbehavOFTESTCTLISSIGNALDIV2CLK:STD_L
7、OGIC;BEGINPROCESS(CLKK)BEGINIFCLKK'EVENTANDCLKK='1'THENDIV2CLK<=NOTDIV2CLK;--(2FENPIN)ENDIF;ENDPROCESS;PROCESS(CLKK,DIV2CLK)BEGINIFCLKK='0'ANDDIV2CLK='0'THENRST_CNT<='1';ELSERST_CNT<='0';ENDIF;ENDPROCESS;LOAD<=NOTDIV2CLK;CNT_EN<=DIV2CLK;ENDBEHAV;寄存器文件：LIBRARYIEEE;USEIEEE.STD_LO
