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1、第6章VHDL顺序语句1libraryieee;useieee.std_logic_1164.all;entityreset_dff2isport(clk,reset:instd_logic;d:instd_logic;q:outstd_logic);endreset_dff2;architecturertlofreset_dff2isbeginprocessbeginwaitonclk,reset;if(reset=‘1’)thenq<=‘0’;elsif（clk’eventandclk=‘1’)thenq<=d;endif;waitonclk,reset;en
2、dprocess;endrtl;2processbeginwaituntilclk’eventandclk=‘1’；if(reset=‘1’)thenq<=‘0’;elseq<=d;endif;endprocess;endrtl;3libraryieee;useieee.std_logic_1164.all;entityclk_generatorisport(clk:outstd_logic);endclk_generator;architectureexampleofclk_generatorisbeginprocessbeginwaitfor125ns;clk
3、<=‘0’;waitfor125ns;clk<=‘1’;endprocess;endrtl;4M时钟发生器4architecturebehaveofexampleissignala,b:std_logic;begina<=‘0’;label1:processbeginwaituntilb=‘1’;a<=‘1’after10ns;waituntilb=‘0’;a<=‘0’after10ns;endprocess;label2:processbeginwaituntila=‘0’;b<=‘0’after10ns;waituntila=‘1’;b<=‘1’after10
4、ns;endprocess;endbehave;waituntil(b=‘1’)for1µs5libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityadderisport(q1,q2:instd_logic_vector(7downto0);cs:instd_logic;q:outstd_logic_vector(7downto0));endadder;architecturebehaveofadderisbeginprocess(cs)beginif(cs=‘1’）
5、thenq<=q1+q2;endif;endprocess;endbehave;使能控制端6entitymux2isport(d0,d1:instd_logic_vector(3downto0);sel:instd_logic;q:outstd_logic_vector(3downto0));endmux2;architecturertlofmux2isbeginprocess(d0,d1,sel)beginif(sel=‘1’）thenq<=d0;elseq<=d1;endif;endprocess;endrtl;选通控制端（二选一）7process(d0,d1
6、,d2,d3,sel)beginif(sel=“00”）thenq<=d0;elsif(sel=“01”)thenq<=d1;elsif(sel=“10”)thenq<=d2;elseq<=d3;endif;endprocess;选通控制端（四选一）8libraryieee;useieee.std_logic_1164.all;entityse7isport(input:instd_logic_vector(3downto0);output:outstd_logic_vector(6downto0));endse7;architecturese7_arcofse7
7、isbeginprocess(input)begincase语句；endprocess;endse7_arc;(1)(0)(6)(2)(3)(5)(4)9caseinputiswhen“0000”=>output<=(‘0’,’1’,’1’,’1’,’1’,’1’,’1’);when“0001”=>output<=(‘0’,’0’,’0’,’0’,’1’,’1’,’0’);when“0010”=>output<=(‘1’,’0’,’1’,’1’,’0’,’1’,’1’);when“0011”=>output<=(‘1’,’0’,’0’,’1’,’1’,’1’,’1
8、’);wh
