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1、现场设计参考题目1、采用文本编辑法，利用VHDL语言实现1位全加器的设计（并行布尔方程法）--并行布尔方程法libraryieee;useieee.std_logic_1164.all;entityAdderFullisport(ai,bi,ci_1:instd_logic;si,ci:outstd_logic);endAdderFull;architectureArcAdderFullofAdderFullisbeginsi<=aixorbixorci_1;ci<=(aiandbi)or(aiandci_1)or(biandci_
2、1);endArcAdderFull;--AdderFull_2.vhdl2、采用文本编辑法，利用VHDL语言实现1位全加器的设计（并行withselectwhen方法）libraryieee;useieee.std_logic_1164.all;entityAdderFull_2isport(ai,bi,ci_1:instd_logic;si,ci:outstd_logic);endAdderFull_2;architectureArcAdderFull_2ofAdderFull_2issignalinstruction:std_
3、logic_vector(2downto0);begininstruction<=ci_1&bi&ai;withinstructionselectsi<='0'when"000",'1'when"001",'1'when"010",'0'when"011",'1'when"100",'0'when"101",'0'when"110",'1'when"111",'Z'whenothers;withinstructionselectci<='0'when"000",'0'when"001",'0'when"010",'1'when"01
4、1",'0'when"100",'1'when"101",'1'when"110",'1'when"111",'Z'whenothers;endArcAdderFull_2;--AdderFull_3.vhd1、采用文本编辑法，利用VHDL语言实现1位全加器的设计（并行whenelse方法）libraryieee;useieee.std_logic_1164.all;entityAdderFull_3isport(ai,bi,ci_1:instd_logic;si,ci:outstd_logic);endAdderFull_3;ar
5、chitectureArcAdderFull_3ofAdderFull_3issignalinGroup:std_logic_vector(2downto0);signaloutGroup:std_logic_vector(1downto0);begininGroup<=ci_1&bi&ai;outGroup<="00"wheninGroup="000"else"01"wheninGroup="001"else"01"wheninGroup="010"else"10"wheninGroup="011"else"01"wheninGr
6、oup="100"else"10"wheninGroup="101"else"10"wheninGroup="110"else"11"wheninGroup="111"else"ZZ";process(outGroup)beginci<=outGroup(1);si<=outGroup(0);endprocess;endArcAdderFull_3;--AdderFull_4.vhd1、利用VHDL语言实现1位全加器的设计（进程顺序语句ifthenelse真值表法）libraryieee;useieee.std_logic_1164
7、.all;entityAdderFull_4isport(ci_1,bi,ai:instd_logic;ci,si:outstd_logic);endAdderFull_4;architectureArcAdderFull_4ofAdderFull_4issignalinGroup:std_logic_vector(2downto0);begininGroup<=ci_1&bi&ai;process(inGroup)variableoutGroup:std_logic_vector(1downto0);beginif(inGroup
8、="000")thenoutGroup:="00";elsif(inGroup="001")thenoutGroup:="01";elsif(inGroup="010")thenoutGroup:="01";elsif(inGroup
