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1、上海交通大学硕士学位论文THERESEARCHANDDESIGN
OFNANO-SCALESRAMINLOWSUPPLYVOLTAGEABSTRACTWiththefeaturesizefallingintonano-scale,theintegrationofchipandtheoperationspeedofthetransistorhavebeenimprovedsignificantly.However,powerconsumptionwillincrease.Duetotheuseofmobilephonesandothermobiledevices,thedemandf
2、orlowingpowerisincreasing.Reducingthesupplyvoltageisaneffectivewaytodecreasingpowerconsumption.However,withthesupplyvoltagereduced,theperformanceofSRAMwillbeinfluenced.Therefore,theresearchofSRAMinlowsupplyvoltageisveryimportant.ThemaintargetofthispaperistoimprovetheperformanceofSRAMinlowsuppl
3、yvoltage.AfterstudyingaboutSRAMstructure,weanalyzetheimpactonSRAMbythemethodoflowingvoltage.Then,somekindsofreadandwriteassistcircuitshavebeenintroduced,andcomparedtheiradvantageanddisadvantage.Theimprovementbynegativebitlineisobvious,anditssideeffectissmall.So,thenegativebit-linevoltage(NBLV)
4、schemebecomesthemainobjectofthispaper.ConventionalNBLVschemegeneratesnegativevoltagebyusingcapacitorcouplingprinciples.Theabsolutevalueofthenegativevoltagewillincreasewithsupplyvoltagerising,Thiswillcausesomeproblem,suchaswritingtheerrordataintothebitcellmistakenly,anddegradingthegateoxidereli
5、abilityofthepass-gatedevice,etc.Inthispaper,apre-dischargenegativebit-linevoltage(PDNBLV)schemeispresentedtosolvetheproblemsarisingfromconventionalNBLV.Byreducingvoltagedifferencebetweenthetwoportsofthecapacitorwhichisusedtogeneratenegativevoltageathighsupplyvoltage,theabsolutevalueofnegativev
6、oltagegeneratedbyII万方数据上海交通大学硕士学位论文PDNBLVislowerthanconventionalNBLV,whilethereisnoeffectatlowsupplyvoltage.Furthermore,weproposetrackingbit-linevoltagecircuittocontrolthetimingofgeneratingnegativevoltageaccurately,andsharedcircuitapproachtosavetheareaandpowerconsumption.TheproposedPDNBLVschem
7、eisimplementedinTSMC40nmCMOStechnology.Theresultshowsthattheschemeimprovesthewriteabilityinlowsupplyvoltage.Thelowestoperationvoltagecanbedropto0.6V.AndPDNBLVmakesthenegativevoltagesuppressedinareasonablerange,whichcansignificantlyexten
