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1、ABSTRACTABSTRACTWiththerapiddevelopmentofsemiconductortechnology,integrationofthechiphasenteredintoSoCera.AM-OLEDdisplaydriverICsisamixedsignalSoCsystem.Thestaticrandomaccessmemory(SRAM),whichisforstoringimageinformation,willbeembeddedinthedisplaydriverICsinordertoimprovesyst
2、em’sperformance.Thesememoryconstituteagreatpartinpowerconsumptionandareaoftheentirechip,andalsoitsspeedrestrictsICs’sdatatransmissionspeed.Therefore,designingahigh-speed,low-powerandsmallmemoryismostimportantfordisplaydriverICs.ThispaperanalyzesthestructureandfunctionofSRAM,a
3、ndthenadetailedanalysisofeachSRAMsub-circuithasbeendone.Byusinghigh-speedlow-powerdesignmethod,aarchitectureofSRAMcircuitisoptimizedaccordingtothespecificrequirementsofdisplaydriverchip.Afterthat,theSRAManditsperipheralcontrolcircuitaredesignedrespectively.IntheSRAMmemorycirc
4、uitdesign,thispaperpresentsalow-powerSRAMdesignwithquiet-bitlinearchitecturebyusingaone-sidedrivingschemeforthewriteoperation.Thebitlineswillbedirectlydrivedwithoutprechargeinthewriteoperation,whichcanpreventtheexcessivefull-swingchargingonthebitlinesandreducethedynamicpowero
5、fmemory.Ontheotherhand,toguaranteecorrectlyreadingdata,thebitlineswillbeprechargedinthereadoperation.Additionally,theopentimeofwordlineisdecreasedtoshortenthedischargingtimeofbitlinesinthewriteoperation,andreducethebitlineswingofinactivecells.Byusingthepre-decodingscheme,amul
6、ti-stagedecodercircuitisdesigned,anditscriticalpathisoptimizedwithlogicaleffort,soastoenablethespeedofdecoderasfastaspossiblewhileminimizingareaandpowerdissipation.Thispaperusestime-divisiontechnology,sothatsingle-portSRAMcanbereadandwrittensimultaneously.Firstly,thepriorityo
7、ftwosignals,MCUwrite/readandlinescan,wouldbedetermined,andthenthetwoparallelsignalswouldbeconvertedinordertobeexecutedinturnbyinternalsingle-portSRAM.Thereforetwoparalleloperationscanbecompletedindependently,andtheconflictsbetweenthemareII万方数据ABSTRACTresolved.SRAMcircuitwith3
8、20×240×18bithasbeendesignedbasedon0.18μmstandardCMOStechnology.There
