实验二加法器的设计与仿真实验报告

《实验二加法器的设计与仿真实验报告》由会员上传分享，免费在线阅读，更多相关内容在学术论文-天天文库。

1、实验二加法器的设计与仿真、实验目的:实现加法器的设计与仿真实验内容1.用逻辑图和VHDL语言设计全加器；2.利用设计的全加器组成串行加法器；3.用逻辑图和VHDL语言设计并行加法器。三、实验步骤。（一）、全加器、串行加法器和并行加法器的逻辑2.串行加法器:3.74283：4位先行进位全加器逻辑框图：74283CNA2B2A)B)77C=>-^c=>-^rCINA1BISUM1oiA2wVVVIISUM2R2SUMSA3SUM4B3COUTuJA4B4r«4BITADDER逻辑图:（二）、全加器、串行加法

2、器和并行加法器的VHDL。1.全加器：LIBRARYieee;USEieee.stdlogic1164.all;LIBRARYwork;ENTITYquanjiaqiISPORT(X:INSTD_LOGIC;Y:INSTD_LOGIC;CIN:INSTD_LOGIC;S:OUTSTDLOGIC;COUT:OUTSTD_LOGIC)；ENDquanjiaqi;ARCHITECTUREbdftypeOFquanjiaqiISSTD_LOGIC;STD_LOGTC;STD_LOGIC;STDLOGIC;SIG

3、NALSYNTHESIZEDJVIRE_OSIGNALSYNTHRSTZED_WTRE_1SIGNALSYNTHESIZED一WIRE一2SIGNALSYNTHESIZEDWIRE3BEGINYANDX;CINANDY;CINANDX;XXORY;0XORCIN;SYNTHESTZED_WTRE_2<=SYNTIIESIZED_WIRE_1<=SYNTHESIZEDWIRE3<=SYNTHES1ZED_W1RE_O<=S〈二SYNTHESIZEDJVIRE_COUT<=SYNTHESTZED_WIRE_

4、1ORSYNTHRSTZRDJVIRE_2ORSYNTHRSTZED_WTRE_3;ENDbdf_type;2.串行加法器:LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYwork;ENTITYchuanxingjiafaqiISPORT(xO:INSTD_LOGIC;yO:INSTD一LOGIC;cin:INSTD_LOGIC;xl:INSTDLOGIC;x2:INSTD_LOGIC;y2:INSTD_LOGIC;x3:INSTD_LOGIC;y3:INST

5、D—LOGIC;yl:INSTD_LOGIC;SO:OUTSTD_LOGIC;si:OUTSTD_LOGIC;s2:OUTSTD_LOGIC;S3:OUTSTD_LOGIC;cout:OUTSTD_LOGIC)；ENDchuanxingjiafaqi;ARCHITECTUREbdf_typeOFchuanxingjiafaqiISCOMPONENTquanjiaqiPORT(X:INSTD_LOGIC;Y:INSTD_LOGIC;CIN:INSTD_LOGIC;S:OUTSTDLOGIC;COUT:OU

6、TSTD_LOGIC);STDJJDGIC;STD_LOGIC;STD^LOGIC;ENDCOMPONENT;SIGNALSYNTHESIZED_WIRE_OSIGNALSYNTHESIZED_WIRE_1SIGNALSYNTHESIZED_WIRE_2BEGINb2v」nst:quanjiaqiPORTMAP(X=>xO,Y=>yO,CIN=>cin,S=>sO,COUT=>SYNTHESIZED_WIRE_O);b2v_instl:quanjiaqiPORTMAP(X=>xl,Y=>yl,CIN=>

7、SYNTHESIZEDWIRE0，S=>sl,COUT=>SYNTHESIZED_WIRE_1);b2v」nst2:quanjiaqiPORTMAP(X=>x2,Y=>y2,CIN=>SYNTHESIZEDWIRE1,S=>s2,COUT=>SYNTHESIZED_WIRE_2);b2v_inst3:quanjiaqiPORTMAP(X=>x3,Y=>y3,CIN=>SYNTHESIZEDWIRE2,S=>s3,COUT=>cout);ENDbdf_type;3.74283：4位先行进位全加器LIBRA

8、RYieee;USEieee.std_logic_1164.all;LIBRARYwork;ENTITY74283_0ISPORT(CININSTD__LOGIC;A1INSTD__LOGIC;A2INSTD__LOGIC;B2INSTD__LOGIC;A3INSTD_LOGIC;A4INSTD__LOGIC;B4INSTD_■LOGIC;B1:INB3:INSUM4COUTSUM1SUM2SUM3)；END742830：STDLOGIC;