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ID：27741394
大小：2.37 MB
页数：19页
时间：2018-12-05
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1、www.ti.com SLWS156−MARCH2004 DSingle-EndedorDifferentialClockFEATURESDD11-BitResolutionD1-GHz−3-dBInputBandwidthDD65-MSPSMaximumSampleRate(7mmx7mmbodysize)D2-VppDifferentialInputRange3.3-VSingleSupplyOperationDD1.8-Vto3.3-VO
2、utputSupplyAPPLICATIONSD400-mWTotalPowerDissipationCellularBaseTransceiverStationReceiveD DTwo’sComplementOutputFormat−HighIFSamplingApplicationsChannelDOn-ChipS/HandDutyCycleAdjustCircuit−CDMA:IS-95,UMTS,CDMA1XD63.3-dBFSSNRand72.9-dBcSFDRat−TDMA:GSM,IS-136,EDGE/UWC-136−WirelessLocalLoopD65MS
3、PSand220-MHzInputPower-DownMode−WidebandBasebandReceiversDESCRIPTIONTheADS5413−11isalowpower,11-bit,65-MSPS,CMOSpipelineanalog-to-digitalconverter(ADC)thatoperatesfrom asingle3.3-Vsupply,whileofferingthechoiceofdigitaloutputlevelsfrom1.8Vto3.3V.Thelownoise,highlinearity,and lowclockjittermake
4、stheADCwellsuitedforhigh-inputfrequencysamplingapplications.On-chipdutycycleadjustcircuit allowstheuseofanon-50%dutycycle.Thiscanbebypassedforapplicationsrequiringlowjitterorasynchronous sampling.Thedevicecanalsobeclockedwithsingleendedordifferentialclock,withoutchangeinperformance.The intern
5、alreferencecanbebypassedtouseanexternalreferencetosuittheaccuracyandlowdriftrequirementsofthe application.Thedeviceisspecifiedoverfulltemperaturerange(−40°Cto+85°C).FUNCTIONALBLOCKDIAGRAMAVDDOVDDPWDVINPVINNREFSELS/HGainGainStageStageΣΣ7StagesA/DA/DD/AD/AA/DD/AΣGainStageFlashA/DVREFT2.25VCML1.
6、8VVREFB1.25VInternalReferenceGenerator2222VBGDigitalErrorCorrectionCLKCLKCDCADCAD[0:10]AGNDOGNDPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstruments semiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.Comm
7、sADCisatrademarkofTexasInstruments. Copyrigh
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