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1、译码器的设计architecturedec_behaveofe1isSignalsel:std_logic_vector(0to3);beginsel(0)<=en;sel(1)<=a(0);sel(2)<=a(1);sel(3)<=a(2);withselselecty<="00000001"when"1000","00000010"when"1001","00000100"when"1010","00001000"when"1011","00010000"when"1100","00100000"when"1101","01000000"
2、when"1110","10000000"when"1111","00000000"whenothers;enddec_behave;编码器的设计libraryIEEE；entityencoder83isport(ind:instd_logic_vector(7downto0)；outd:outstd_logic_vector(2downto0));end;architecturebehaveofencoder83isbeginprocess(ind)beginifind(7)=‘1'thenoutd<="111";elsifind(6)=‘
3、1'thenoutd<="110";elsifind(5)=‘1'thenoutd<="101";elsifind(4)=‘1'thenoutd<="100";elsifind(3)=‘1'thenoutd<="011";elsifind(2)=‘1'thenoutd<="010";elsifind(1)=‘1'thenoutd<="001";elsifind(0)=‘1'thenoutd<="000";elseoutd<="000";endif;endprocess;endbehave;数据选择器的设计LIBRARYIEEE;……；ENTI
4、TYE3ISPORT(A,B,C,D:INSTD_LOGIC_VECTOR(3DOWNTO0);S:INSTD_LOGIC_VECTOR(0TO1)；Z:OUTSTD_LOGIC_VECTOR(3DOWNTO0)）；END；ARCHITECTURECONC_BEHAVEOFE3ISBEGINZ<=AWHENS="00"ELSEBWHENS="01"ELSECWHENS="10"ELSEDWHENS="11"ELSE"0000"；ENDCONC_BEHAVE；比较器：设计八位比较器，相等时输出为1，否则输出为0libraryieee；entit
5、ycompareisport(a,b:instd_logic_vector(7downto0);y:outstd_logic);endcompare;architecturebehaveofcompareisbeginprocesss(a,b)Beginif(a=b)theny<='1';elsey<='0';endif;endprocess;endbehave;求补器：求补器的输入信号为a（7..0），输出信号为b（7..0），设a（7）和b（7）为符号位。libraryieee;useieee.std_logic_1164.all;use
6、ieee.std_logic_unsigned.all;entitycomplementisport(a:instd_logic_vector(7downto0);b:outstd_logic_vector(7downto0));endcomplement;architecturebehaveofcomplementisbeginprocess(a)beginif(a(7)='0')thenb<=a;elseb<='1'&(nota(6downto0)+'1');endif;endprocess;endbehave;单向总线缓冲器的设计LIB
7、RARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYe7ISport(enable:INSTD_LOGIC;datain:INSTD_LOGIC_VECTOR(7DOWNTO0);dataout:OUTSTD_LOGIC_VECTOR(7DOWNTO0));END;ARCHITECTUREbhvOFe7ISBEGINPROCESS(enable,datain)BEGINIFenable='1'THENdataout<=datain;ELSEdataout<="ZZZZZZZZ";ENDIF;ENDPROCESS
8、;ENDbhv;双向总线缓冲器的设计libraryieee;……ENTITYe8ISport(en,dr:instd_logic;a,b:inoutstd_logi
