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1、姓名和学号江帆2010042020009丁康一2010042020003侯宝义2010042010003选择设计一，设计三，设计五设计一七段显示译码器设计；要求对未用编码1010~1111进行讨论我从最小成本考虑，所以为了简化电路，对10到15的未用编码设为d，真值表为ENDCBASEGASEGBSEGCSEGDSEGESEGFSEGG000000001000011111101000101100001001011011011001111110011010001100111010110110111011010111111011111100001100011111
2、1111001111101111010~1111ddddddd由上述的真值表可以得到表达式为有上述的表达式在quartus中连接电路如下仿真得到的波形是然后用软件生成的对应的Verilog程序如下//Copyright(C)1991-2008AlteraCorporation//YouruseofAlteraCorporation'sdesigntools,logicfunctions//andothersoftwareandtools,anditsAMPPpartnerlogic//functions,andanyoutputfilesfromanyofth
3、eforegoing//(includingdeviceprogrammingorsimulationfiles),andany//associateddocumentationorinformationareexpresslysubject//tothetermsandconditionsoftheAlteraProgramLicense//SubscriptionAgreement,AlteraMegaCoreFunctionLicense//Agreement,orotherapplicablelicenseagreement,including,//w
4、ithoutlimitation,thatyouruseisforthesolepurposeof//programminglogicdevicesmanufacturedbyAlteraandsoldby//Alteraoritsauthorizeddistributors.Pleaserefertothe//applicableagreementforfurtherdetails.//PROGRAM"QuartusII"//VERSION"Version8.1Build16310/28/2008SJFullVersion"//CREATEDON"SatJu
5、n0917:14:122012"module11(A,B,C,D,SA,SB,SC,SD,SE,SF,SG);inputA;inputB;inputC;inputD;outputSA;outputSB;outputSC;outputSD;outputSE;outputSF;outputSG;wiregdfx_temp0;wireSYNTHESIZED_WIRE_0;wireSYNTHESIZED_WIRE_1;wireSYNTHESIZED_WIRE_2;wireSYNTHESIZED_WIRE_35;wireSYNTHESIZED_WIRE_4;wireS
6、YNTHESIZED_WIRE_36;wireSYNTHESIZED_WIRE_37;wireSYNTHESIZED_WIRE_12;wireSYNTHESIZED_WIRE_13;wireSYNTHESIZED_WIRE_14;wireSYNTHESIZED_WIRE_18;wireSYNTHESIZED_WIRE_19;wireSYNTHESIZED_WIRE_24;wireSYNTHESIZED_WIRE_25;wireSYNTHESIZED_WIRE_26;wireSYNTHESIZED_WIRE_30;wireSYNTHESIZED_WIRE_31;
7、wireSYNTHESIZED_WIRE_32;assignSYNTHESIZED_WIRE_0=A&gdfx_temp0;assignSA=SYNTHESIZED_WIRE_0
8、SYNTHESIZED_WIRE_1
9、D;assignSB=SYNTHESIZED_WIRE_2
10、SYNTHESIZED_WIRE_35
11、SYNTHESIZED_WIRE_4;assignSYNTHESIZED_WIRE_2=A&gdfx_temp0;assignSYNTHESIZED_WIRE_4=SYNTHESIZED_WIRE_36&SYNTHESIZED_WIRE_37;as
12、signSC=gdfx_temp0
13、S
