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ID:12769675
大小:211.50 KB
页数:4页
时间:2018-07-18
《xilinx 双口ram ipcore teset(vhdl)》由会员上传分享,免费在线阅读,更多相关内容在行业资料-天天文库。
1、Xilinx双口RAMIpcoreTeset(VHDL)CPLD/FPGA2010-03-1911:39:14阅读77评论0字号:大中小 这几天能Xilinx的双口RAMCORE,终于能好了。现将代码和时序贴出来。代码:LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.all;USEieee.numeric_std.ALL; ENTITYDoubleRamTestISENDDoubleRamTest; ARCHIT
2、ECTUREbehaviorOFDoubleRamTestIS --ComponentDeclarationfortheUnitUnderTest(UUT) COMPONENTIPTest PORT( clka:IN std_logic; ena:IN std_logic; wea:IN std_logic_vector(0downto0); addra:IN std_logic_vector(9downto0);
3、 dina:IN std_logic_vector(15downto0); douta:OUT std_logic_vector(15downto0); clkb:IN std_logic; enb:IN std_logic; web:IN std_logic_vector(0downto0); addrb:IN std_logic_vector(9downto0); dinb:IN std_logic_vector
4、(15downto0); doutb:OUT std_logic_vector(15downto0) ); ENDCOMPONENT; --Inputs signalclka:std_logic:='0'; signalena:std_logic:='0'; signalwea:std_logic_vector(0downto0):=(others=>'0'); signaladdra:std_logic_vector(9downto0):=(other
5、s=>'0'); signaldina:std_logic_vector(15downto0):=(others=>'0'); signalclkb:std_logic:='0'; signalenb:std_logic:='0'; signalweb:std_logic_vector(0downto0):=(others=>'0'); signaladdrb:std_logic_vector(9downto0):=(others=>'0'); signaldinb:std_logic_
6、vector(15downto0):=(others=>'0'); signalcount:std_logic_vector(15downto0):=(others=>'0'); --Outputs signaldouta:std_logic_vector(15downto0); signaldoutb:std_logic_vector(15downto0); --Clockperioddefinitions constantclka_period:time:=1us; consta
7、ntclkb_period:time:=1us; BEGIN --InstantiatetheUnitUnderTest(UUT) uut:IPTestPORTMAP( clka=>clka, ena=>ena, wea=>wea, addra=>addra, dina=>dina, douta=>douta, clkb=>clkb, enb=>enb,
8、 web=>web, addrb=>addrb, dinb=>dinb, doutb=>doutb ); ena<='1'; enb<='1'; --Clockprocessdefinitions clka_process:process begin clka<='0'; waitforclka_period/2; clka<='1'; waitforclka_period/2; count<
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