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1、4_16译码器设计libraryieee;useieee.std_logic_1164.all;entitydecode4_16isport(a:instd_logic_vector(3downto0);y:outstd_logic_vector(15downto0));end;architectureoneofdecode4_16isbeginprocess(a)begincaseaiswhen"0000"=>y<="1111111111111110";when"0001"=>y<="1111111111111101";when"0010"
2、=>y<="1111111111111011";when"0011"=>y<="1111111111110111";when"0100"=>y<="1111111111101111";when"0101"=>y<="1111111111011111";when"0110"=>y<="1111111110111111";when"0111"=>y<="1111111101111111";when"1000"=>y<="1111111011111111";when"1001"=>y<="1111110111111111";when"1010"=>
3、y<="1111101111111111";when"1011"=>y<="1111011111111111";when"1100"=>y<="1110111111111111";when"1101"=>y<="1101111111111111";when"1110"=>y<="1011111111111111";when"1111"=>y<="0111111111111111";whenothers=>y<="ZZZZZZZZZZZZZZZZ";endcase;endprocess;end;VHDL设计256_8ROM实验源程序librar
4、yieee;useieee.std_logic_1164.all;entityrom256_8isport(address:instd_logic_vector(7downto0);relt:outstd_logic_vector(7downto0));end;architectureoneofrom256_8issignalcs:std_logic_vector(3downto0);signaladdress1:std_logic_vector(3downto0);signalallen:std_logic_vector(15downto0
5、);componentdecode4_16port(a:instd_logic_vector(3downto0);y:outstd_logic_vector(15downto0));endcomponent;componentrom16_8port(addr:instd_logic_vector(3downto0);en:instd_logic;data:outstd_logic_vector(7downto0));endcomponent;begincs<=address(7downto4);address1<=address(3downt
6、o0);yima:decode4_16portmap(cs,allen);gesrom16_8:fornin0to15generatesrom16_8:rom16_8portmap(address1,allen(n),relt);endgenerate;end;VHDL16-8ROM设计源程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityrom16_8isport(addr:instd_logic_vector(3downto0);en:
7、instd_logic;data:outstd_logic_vector(7downto0));end;architectureoneofrom16_8istypememoryisarray(0to15)ofstd_logic_vector(7downto0);signaldata1:memory:=("01000001","01000010","01000011","01000100","01000101","01000110","01000111","01001000","01001001","01001010","01001011","
8、01001100","01001101","01001110","01001111","01010001");signaladdr1:integerrange0to
