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1、第4章用VHDL程序实现常用逻辑电路4.1组合逻辑电路设计4.1.1基本逻辑门libraryieee;useiee.std」ogic_l164.all;entityjbmisport(a,b:inbit;fl,f2,f3,f4,f5,f:outbit);endjbm;architectureaofjbmisbeginfl<=aandb;f2<=aorb;f<=nota;f3<=anandb;f4<=anorb;f5<=not(axorb);end;4.1.2三态门-构成与门--构成或门••构成非门..构成与非门-构成异或门-构成异或非门即同门libraryieee;
2、useieee.std_logic_1164.all;entitytri_sisport(enable:instd」ogic;datain:instdjogic_vector(7downto0);dataout:outstd_logic_vector(7downtoO));endtri_s;architecturebhvoftri_sisbeginprocess(enable,datain)beginifenable二Tthendataout<=datain;elsedataout<="ZZZZZZZZM;endif;endprocess;endbhv;4.1.33
3、・8译码器libraryieee;useieee.std_logic_1164.all;entitydecoder3_8isport(a,b,c,g1,g2a,g2b:inskUogic;y:outs(d」ogic_vector(7downto0));enddecoder3_8;architectureaofdecoder3_8issignaldz:std_logic_vector(2downto0);begindz<=c&b&a;process(dz,g1,g2a,g2b)beginif(g1='1'andg2a='0'andg2b='0')thencasedzi
4、swhen”()()()”二〉yv=”11111110”；when,,00r,=>y<=Hllllll()l";when,,010,,=>y<=,rl1111011";when••011"=>y<=,,111101ir,;when"1()()"=>y<=Hlll()llll";when”1()1”=〉y<=,,ll()Illll";when•,110"=>y<=,,101111ir,;when,,1H,,=>yVOllIllll”；whenothers=>y<="XXXXXXXXM;endcase;elseyv二Tlllllll”；endif;endprocess;
5、4.1.4优先编码器libraryieee;useieee.std_logic_l164.allentitycoderisport(din:instd_logic_vector(0to7);output:outstd_logic_vector(0to2));endcoder;architecturebehaveofcoderissignalsint:stdjogic_vevtor(4downto0);beginprocess(din)beginif(din(7)=,0,)thenoutput<=”000”;elsif(din(6)='O')thenoutputv二T
6、OO”；elsif(din(5)='0')thenoutputv二”010”；elsif(din(4)='O')thenoutput<="HO";elsif(din(3)='0')thenoutputv二"001”；elsif(din(2)='O')thenoutput<=”101”；elsif(din(l)='()*)thenoutputv二”011";elseoutput<=Hllln;endif;endprocess;endbehav;4.1.57段码译码器libraryieee;useieee.std」ogic_l164.allentitydecl7sisp
7、ort(a:ins(d」ogic_vec(or(3clownto0);led7s:outstd_logic_vecior(6downto0));enddecl7s;architecturebehaveofdccl7sisbeginprocess(a)begincaseaiswhen”0000”=>led7s<=”0111111”;when”0001”=>led7s<=,,0000110,,;when”0010”=>led7s”1011011”;when”0011"=>led7s<=T001111”；when”0100"=>led7sv=”1100110”；whe
