VHDL 六十进制计数器.doc

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1、libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount60isport(clk,clk0,cin,bcd1wr,bcdswr:instd_logic;datain:instd_logic_vector(3downto0);co:outstd_logic;a,b,c,d,e,f,g:outstd_logic;sel:outstd_logic_vector(2to0));endcount60;architectureartofcount60issignalbc

2、d1n:std_logic_vector(3downto0);signalbcdsn:std_logic_vector(2downto0);signaloutda:std_logic_vector(6downto0);beginprocess(clk,bcd1wr)beginif(bcd1wr='1')thenbcd1n<=datain;elsif(clk'eventandclk='1')thenif(cin='1')thenif(bcd1n=9)thenbcd1n<="0000";elsebcd1n<=bcd1n+1;endif;endif;endif;end

3、process;process(clk,bcdswr)beginif(bcdswr='1')thenbcdsn<=datain(2downto0);elsif(clk'eventandclk='1')thenif(cin='1'andbcd1n=9)thenif(bcdsn=5)thenbcdsn<="000";elsebcdsn<=bcdsn+1;endif;endif;endif;endprocess;process(bcd1n,bcdsn,cin)beginif(bcd1n=9andbcdsn=5andcin='1')thenco<='1';elseco<

4、='0';endif;endprocess;process(clk0,bcd1n,bcdsn)beginifclk0='1'thensel<="000";casebcd1niswhen"0000"=>outda<="";when"0001"=>outda<="";when"0010"=>outda<="";when"0011"=>outda<="";when"0100"=>outda<="";when"0101"=>outda<="";when"0110"=>outda<="";when"0111"=>outda<="";when"1000"=>outda<="

5、";when"1001"=>outda<="";whenothers=>outda<="";endcase;elsesel<="110";casebcdsniswhen"000"=>outda<="";when"001"=>outda<="";when"010"=>outda<="";when"011"=>outda<="";when"100"=>outda<="";when"101"=>outda<="";whenothers=>outda<="";endcase;endif;a<=outda(6);b<=outda(5);c<=outda(4);d<=out

6、da(3);e<=outda(2);f<=outda(1);g<=outda(0);endprocess;endart;