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1、__________________________________________________1．以下是一位全加器的VHDL设计，试补充完整。libraryieee;--半加器设计useieee.std_logic_1164.all;entityh_adderisport(a,b:instd_logic;co,so:outstd_logic);endh_adder;architecturefh1ofh_adderisbeginso<=not(axor(notb));co<=aandb;endarchit
2、ecturefh1;libraryieee;--或门设计useieee.std_logic_1164.all;entityor2aisport(a,b:instd_logic;c:outstd_logic);endor2a;architecturertlofor2aisbeginc<=aorbafter10ns;endrt;libraryieee;--全加器设计useieee.std_logic_1164.all;entityf_adderISport(ain,bin,cin:instd_logic;cout
3、,sum:outstd_logic);endentityf_adder;architecturefd1OFf_adderIScomponenth_adderport(a,b:instd_logic;co,so:outstd_logic);endcomponent;componentor2a____________________________________________________________________________________________________port(a,b:ins
4、td_logic;c:outstd_logic);endcomponent;signald,e,f:std_logic;beginu1:h_adderportmap(a=>ain,b=>bin,co=>d,so=>e);u2:h_adderportmap(a=>e,b=>cin,co=>f,so=>sum);u3:or2aportmap(a=>d,b=>f,c=>cout);endarchitecturefd1;2．以下是含有使能端且具有同步清零的加减计数器的VHDL设计，试补充完整。libraryieee;
5、useieee.std_logic_1164.all;entitycounterisport(updown,enable,clear,clk:instd_logic;q:outintegerrange0to255);endcounter;architectureaofcounterisbeginprocess(clk)variablecnt:integerrange0to（7）;variabledirection:（8）;beginif(updown='1')thendirection:=1;else（9）e
6、ndif;if(clk'eventandclk='1')thenifclear='0'thencnt:=0;____________________________________________________________________________________________________elseifenable='1'then（10）endif;endif;endif;q<=cnt;endprocess;enda;______________________________________
7、______________________________________________________________(7)255(8)integer(9)direction:=-1；(10)cnt:=cnt+direction____________________________________________________________________________________________________1．以下是8位分频器程序设计LIBRARYIEEE;USEIEEE.STD_LO
8、GIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPULSEISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);FOUT:OUTSTD_LOGIC);END;ARCHITECTUREoneOFPULSEISSIGNALFULL:STD_LOGIC;BEGINP_REG:PROCESS(CLK)V
