1、单个数码管verilog程序module seg1(clk,a,seg);input clk;output a;output [7:0] seg;reg [7:0] seg;reg a; reg [23:0]cnt1;reg [3:0]cnt2; always @(posedgeclk) begin a=1; end always @(posedgeclk) begin if(cnt1!=24'hffffff) begin cnt1<=cnt1+1; end
2、 else begin cnt1<=0; cnt2<=cnt2+1; if(cnt2!=10) begin case(cnt2) 4'd1: seg<=8'b10000010; 4'd2: seg<=8'b10111110; 4'd3: seg<=8'b00100011; 4'd4: seg<=8'b00011110; 4'd5: seg
3、<=8'b01001010; 4'd6: seg<=8'b01000010; 4'd7: seg<=8'b10101110; 4'd8: seg<=8'b00000010; 4'd9: seg<=8'b00001010; default:seg<=8'b11111111; endcase end else cnt2<=0; end end
