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1、实验一.半加器，全加器的设计1，半加器的设计，方法一libraryieee;useieee.std_logic_1164.all;entityh_adder1isport(a,b:instd_logic;c,s:outstd_logic);endentityh_adder1;architectureoneofh_adder1isbegins<=axorb;c<=aandb;endarchitectureone;运行结果：方法二：运行结果：2，全加器的设计方法一：libraryieee;useieee.std_logic_1164.all;entit
2、yf_adder1isport(a,b,cin:instd_logic;sum,cout:outstd_logic);endentityf_adder1;architecturearchoff_adder1iscomponenth_adder1port(a,b:instd_logic;s,c:outstd_logic);endcomponent;componentor23port(a,b:instd_logic;c:outstd_logic);endcomponent;signalx:std_logic_vector(0to2);beginu1:h
3、_adder1portmap(a,b,x(1),x(0));u2:h_adder1portmap(x(1),cin,sum,x(2));u3:or23portmap(a=>x(0),b=>x(2),c=>cout);endarch;运行结果：方法二：运行结果：实验二.四选一数据选择器的设计1用case语句：libraryieee;useieee.std_logic_1164.all;entitymux4_1aisport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1dow
4、nto0);q:outstd_logic_vector(3downto0));endmux4_1a;architecturearchofmux4_1aisbeginprocess(A,B,C,D,sel)begincaseseliswhen"00"=>q<=A;when"01"=>q<=B;when"10"=>q<=C;when"11"=>q<=D;whenothers=>null;endcase;endprocess;endarch;运行结果：2，用if语句设计：libraryieee;useieee.std_logic_1164.all;ent
5、itymux4_1bisport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0));endmux4_1b;architecturearchofmux4_1bisbeginprocess(A,B,C,D,sel)beginIFsel="00"thenq<=A;elsifsel="01"thenq<=B;elsifsel="10"thenq<=C;elsifsel="11"thenq<=D;endi
6、fendprocess;endarch;用with语句设计：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymux4_1cisport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0));endmux4_1c;architecturearchofmux4_1cisbeginwithselsele
7、ctq<=Awhen"00",Bwhen"01",Cwhen"10",Dwhen"11","ZZ"whenothers;endarch;运行结果：4，用when语句设计：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymux4_1disport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0))
8、;endmux4_1d;architecturearchofmux4_1disbeginq<=Awhensel="00"e
