2016年北邮数电实验报告.doc

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1、..数字电路与逻辑设计实验报告学院：电子工程学院班级：：.....学号：班序号：.....目录（一）实验名称及实验任务要求·························1（二）模块端口说明及连接图····························21.1实验三(3)模块端口说明····························21.2实验三(3)连接图···································22.1实验四模块端口说明·······························22.2实验四连接图············

2、··························2（三）原理图或VHDL代码································31.实验一(2)原理图·····································3.....2.实验三(3)VHDL代码··································43.实验四VHDL代码····································7（三）仿真波形··············································101.实验一(2

3、)仿真波形····································102.实验三(3)仿真波形····································113.实验四仿真波形·······································11（四）仿真波形分析.....··········································111.实验一(2)仿真波形分析································112.实验三(3)仿真波形分析·······················

4、·········113.实验四仿真波形分析····································11（六）故障及问题分析·······································12（七）总结和结论············································13.....（一）实验名称及实验任务要求实验一名称：QuartusII原理图输入法设计与实现实验任务要求：EDA基础实验1（1）、（2）、（3）必做，选做VHDL实现加法器。实验二名称：用VHDL设计与实现组合逻辑电路实验任务要求：四人表决器、

5、8421码转格雷码、数码管译码器（下载测试）。实验三名称：用VHDL设计与实现时序逻辑电路实验任务要求：分频器、8421十进制计数器、将分频器/8421十进制计数器/数码管译码器3个电路进行连接并下载。实验四名称：用VHDL设计与实现相关电路.....实验任务要求：数码管动态扫描控制器、点阵扫描控制器。（二）.....（二）模块端口说明及连接图1.1实验三(3)模块端口说明cp：时钟信号输入；rst：8421十进制计数器异步置位；c[6...0]：七段二极管数码管显示；cat[7...0]：数码管显示。1.2实验三(3)连接图2.1实验四模块端口说明cp：时钟信号输

6、入；rst：8421计数器异步复位；lgt[6...0]：七段二极管数码管显示；.....cat[7...0]：数码管显示。2.2实验四连接图（二）.....（二）原理图或VHDL代码1.实验一(2)原理图半加器：全加器：2.实验三(3)VHDL代码//分频器部分libraryieee;.....useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitydiv_12isport(.....cp:instd_logic;clk1:outstd_

7、logic);enddiv_12;architectureaofdiv_12issignaltmp:integerrange0to11;beginprocess(cp)beginif(cp'eventandcp='1')theniftmp=11thentmp<=0;elsetmp<=tmp+1;endif;iftmp<=5thenclk1<='0';elseclk1<='1';endif;endif;endprocess;enda;//8421十进制加法器部分libraryieee;useieee.std_logic_1164.all;.....useieee.