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1、数字电路与逻辑设计基于VHDL的数字逻辑设计常用组合逻辑电路设计常用时序逻辑电路设计VHDL程序设计规范组合逻辑电路设计分析逻辑问题，抽象输入、输出逻辑变量。列真值表、写函数表达式。采用基本门电路、PLD实现。实体描述ENTITY__entity_nameISPORT(__input_name:INSTD_LOGIC;__input_vector_name:INSTD_LOGIC_VECTOR(__highdownto__low);__output_name,:OUTSTD_LOGIC);__output_vector_n
2、ame:OUTSTD_LOGIC_VECTOR(__highdownto__low);END__entity_name;ARCHITECTUREaOF__entity_nameISSIGNAL__signal_name:STD_LOGIC;BEGIN--ProcessStatement--ConcurrentProcedureCall--ConcurrentSignalAssignment--ConditionalSignalAssignment--SelectedSignalAssignment--ComponentIn
3、stantiationStatement--GenerateStatementENDa;结构体描述（1）编码器（2）译码器（3）比较器（4）数据选择器（5）三态输出电路一、常用组合逻辑电路设计（1）编码器A6A7A5A4A3A2A1A0Y2Y1Y08×3编码器ENA7A6A5A4A3A2A1A0Y2Y1Y00000000100000000010001000001000100000100001100010000100001000001010100000011010000000111libraryieee;useieee.st
4、d_logic_1164.all;entitybmqisport(A:instd_logic_vector(7downto0);En:instd_logic;Y:outstd_logic_vector(2downto0));endbmq;architecturem1ofbmqissignalsel:std_logic_vector(8downto0);beginsel<=En&A;withselselectY<="000"when"100000001","001"when"100000010","010"when"1000
5、00100","011"when"100001000","100"when"100010000","101"when"100100000","110"when"101000000","111"when"110000000","000"whenothers;endm1;architecturem2ofbmqissignalsel:std_logic_vector(8downto0);beginProcess(En,A)BeginIfEn='1'thenifA="00000001"thenY<="000";elsifA="00
6、000010"thenY<="001";elsifA="00000100"thenY<="010";elsifA="00001000"thenY<="011";elsifA="00010000"thenY<="100";elsifA="00100000"thenY<="101";elsifA="01000000"thenY<="110";elseY<="111";endif;ElseY<="000";endif;endprocess;endm2;（2）译码器A.3－8译码器3×8译码器A6A7A5A4A3A2A1A0Y2Y
7、1Y0ENlibraryieee;useieee.std_logic_1164.all;entityymqisport(Y:instd_logic_vector(2downto0);EN:instd_logic;A:outstd_logic_vector(7downto0));endymq;architecturem1ofymqissignalsel:std_logic_vector(3downto0);beginsel<=En&Y;withselselectA<="00000001"when"1000","0000001
8、0"when"1001","00000100"when"1010","00001000"when"1011","00010000"when"1100","00100000"when"1101","01000000"when"1110","10000000"when"1111","11111111"whe
