VHDL语言 四选一数据选择器 多种描述.doc

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1、使用if_then语句来描述四选一数据选择器libraryieee;useieee.std_logic_1164.all;entityzeisport(s0,s1:instd_logic;a,b,c,d:instd_logic;y:outstd_logic);endze;architectureabofzeissignals:std_logic_vector(1downto0);begins<=s1&s0;process(s)beginifs<="00"theny<=a;elsifs<="01"the

2、ny<=b;elsifs<="10"theny<=c;elsey<=d;endif;endprocess;endab;使用case语句来描述四选一数据选择器libraryieee;useieee.std_logic_1164.all;entityxuanisport(s0,s1:instd_logic;a,b,c,d:instd_logic;y:outstd_logic);endxuan;architectureabofxuanissignals:std_logic_vector(1downto0);

3、begins<=s1&s0;process(s)begincasesiswhen"00"=>y<=a;when"01"=>y<=b;when"10"=>y<=c;when"11"=>y<=d;whenothers=>null;endcase;endprocess;endab;使用when_else语句来描述四选一数据选择器libraryieee;useieee.std_logic_1164.all;entityxuanisport(s0,s1:instd_logic;a,b,c,d:instd_log

4、ic;y:outstd_logic);endxuan;architectureabofxuanissignals:std_logic_vector(1downto0);begins<=s1&s0;y<=awhens<="00"elsebwhens<="01"elsecwhens<="10"elsed;endab;