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1、DesigningofAdderLecturer：Prof.WangMingjiangDate:Theme：AlgorithmofAdder1.FullAdderSum=A^B^CinCout=A&B+B&Cin+A&Cindefination:carrydelete:D=~A&~Bcarrypropagate:P=A^Bcarrygenerate:G=A&B1.FullAddermodulefulladder(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;assignsum=a^b^cin;assigncout=a&b
2、a&c
3、
4、b&c;endmodulemodulefulladder(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;wirew1,w2,w3,w4;xoru1(w1,a,b);xoru2(sum,w1,cin);oru3(w2,a,b);andu4(w3,cin,w2);andu5(w4,a,b);oru6(cout,w3,w4);endmodule2.Ripple-carryAdder2.Ripple-carryAdderCarry-ChainofanRCAimplementedusingmultiplexerfromthestandard
5、celllibrary:2.Ripple-carryAddermodulerca_4bits(a,b,cin,sum,cout);input[3:0]a,b;inputcin;output[3:0]sum;outputcout;fulladderu1(a[0],b[0],cin,sum[0],carry[0]);fulladderu2(a[1],b[1],carry[0],sum[1],carry[1]);fulladderu3(a[2],b[2],carry[1],sum[2],carry[2]);fulladderu4(a[3],b[3],carry[2],sum[3],
6、cout);endmodule2.Ripple-carryAddermodulerca_4bits(a,b,cin,sum,cout);input[3:0]a,b;inputcin;output[3:0]sum;outputcout;reg[3:0]sum,carry;integerI;always@(a,b,cin)begincarry[0]=cin;for(i=0;i<4;i=i+1)begincarry[i+1]=(a[i]&b[i])
7、((a[i]^b[i])&carry[i]);sum[i]=a[i]^b[i]^carry[i];endendassigncout=c
8、arry[3];endmodule3.Carry-SkipAdderanotherformoffulladdercarrypropagate:P=A^Bcarrygenerate:G=A&BCo=G
9、(P&Ci)S=P^Cimodule(a,b,ci,co,s);inputa,b,ci;ouputco,s;wirep=a^b;wireg=a&b;assignco=g
10、(p&ci);assigns=p^ci;endmoduleS03.Carry-SkipAdder3.Carry-SkipAddermodulecsa_4bit(a,b,ci,s,co);input[3:0]a,b
11、;inputci;outputco;output[3:0]s;wire[3:0]g,p;assigng=a&b;assignp=a&b;……(Itisyourtimetomakethecodecomplete)……endmodule4.MulitbitcarryskipAddertadder=tsetup+Mtcarry+(N/M-1)tbypass+(M-1)tcarry+tsum4.Mulitbitcarry-skipAddermodulecsa_16bit(a,b,ci,s,co);input[15:0]a,b;inputci;outputco;output[15:0]
12、s;wire[3:1]wnet;csa_4bit(a[3:0],b[3:0],ci,s[3:0],wnet[1]);csa_4bit(a[7:4],b[7:4],wnet[1],s[7:4],wnet[2]);csa_4bit(a[11:8],b[11:8],wnet[2],s[11:8],wnet[3]);csa_4bit(a[15:12],b[15:12],wnet[3],s[15:12],co);endmoduleCarry-skipAdderVSRipplecarryaddertadder=ts
