5、现。四位比较器VHDL源文件: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity comp4 is port (A:in std_logic_vector(3 downto 0); B:in std_logic_vector(3 downto 0); M,G,L:out std_logic); end comp4; architecture behave o
6、f comp4 is begin p1: process(A,B) beginif (A>B) then G<='1';M<='0';L<='0'; elsif (A