VHDL流水线加法器.doc

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1、可编程实验报告实验报告要求：1、任务的简单描述2、画出电路图3、写出源代码4、仿真结果5、分析和讨论1、3-8译码器源代码：LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;USEieee.std_logic_signed.all;ENTITYdc38ISPORT(sel:instd_logic_vector(2downto0);y:outstd_logic_vector(7downto0));ENDdc38;ARCHITECTUREbehav

2、iorOFdc38ISBEGINy<="11111110"WHENsel="000"else"11111101"WHENsel="001"else"11111011"WHENsel="010"else"11110111"WHENsel="011"else"11101111"WHENsel="100"else"11011111"WHENsel="101"else"10111111"WHENsel="110"else"01111111"WHENsel="111"else"ZZZZZZZZ";ENDbehavior;仿真结果：一位全

3、加器ABCISCO0000000110010100110110010101011100111111四级流水加法器一位全加器第一级锁存器第三级锁存器一位全加器第二级锁存器一位全加器第四级锁存器一位全加器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityadderisport(clk,rst:instd_logic;a,b:instd_logic_vector(3downto

4、0);sum:outstd_logic_vector(3downto0);c:outstd_logic);endentityadder;architecturedepictofadderissignalreg1:std_logic_vector(7downto0);signalreg2:std_logic_vector(6downto0);signalreg3:std_logic_vector(5downto0);beginbit0:process(clk,rst)beginif(rst='1')thenreg1<="0000

5、0000";elsif(rising_edge(clk))thenreg1(0)<=a(0)xorb(0);reg1(1)<=a(0)andb(0);reg1(2)<=a(1);reg1(3)<=b(1);reg1(4)<=a(2);reg1(5)<=b(2);reg1(6)<=a(3);reg1(7)<=b(3);endif;endprocessbit0;bit1:process(clk,rst)beginif(rst='1')thenreg2<="0000000";elsif(rising_edge(clk))thenre

6、g2(0)<=reg1(0);reg2(1)<=reg1(1)xorreg1(2)xorreg1(3);reg2(2)<=(reg1(1)andreg1(2))or(reg1(1)andreg1(3))or(reg1(2)andreg1(3));reg2(6downto3)<=reg1(7downto4);endif;endprocessbit1;bit2:process(clk,rst)beginif(rst='1')thenreg3<="000000";elsif(rising_edge(clk))thenreg3(1do

7、wnto0)<=reg2(1downto0);reg3(2)<=reg2(2)xorreg2(3)xorreg2(4);reg3(3)<=(reg2(2)andreg2(3))or(reg2(2)andreg2(4))or(reg2(3)andreg2(4));reg3(5downto4)<=reg2(6downto5);endif;endprocessbit2;bit3:process(clk,rst)beginif(rst='1')thensum<="0000";c<='0';elsif(rising_edge(clk))

8、thensum(2downto0)<=reg3(2downto0);sum(3)<=reg3(3)xorreg3(4)xorreg3(5);c<=(reg3(3)andreg3(4))or(reg3(3)andreg3(5))or(reg3(4)andreg3(5));end