4、1add_ine d summ add_out f yxx y h_add suma_out x y h_addsum a_out 图3-1半加器原理图实现1位半减器VHDL程序。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_addISPORT(x,y:INSTD_LOGIC;a_out,sum:OUTSTD_LOGIC);ENDENTITYh_add;ARCHITECTUREadd0OFh_addISSIGNALs:STD_LOGIC_VECTOR(1DOWNTO0);BEGINs<=x&y;PROCESS(s)B