chapter6.ppt

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1、DigitalIntegratedCircuitsADesignPerspectiveDesigningCombinationalLogicCircuitsJanM.RabaeyAnanthaChandrakasanBorivojeNikolićNovember2002.1Combinationalvs.SequentialLogicCombinationalSequentialOutput=f(In)Output=f(In,PreviousIn)2StaticCMOSCircuitAteverypointintime(exceptduringthe

2、switchingtransients)eachgateoutputisconnectedtoeitherVDDorVssviaalow-resistivepath.TheoutputsofthegatesassumeatalltimesthevalueoftheBooleanfunction,implementedbythecircuit(ignoring,onceagain,thetransienteffectsduringswitchingperiods).Thisisincontrasttothedynamiccircuitclass,whic

3、hreliesontemporarystorageofsignalvaluesonthecapacitanceofhighimpedancecircuitnodes.3StaticComplementaryCMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOSonlyNMOSonlyPUNandPDNareduallogicnetworks……4NMOSTransistorsinSeries/ParallelConnectionTransistorscanbethoughtasaswitchcontrol

4、ledbyitsgatesignalNMOSswitchcloseswhenswitchcontrolinputishigh5PMOSTransistorsinSeries/ParallelConnection6ThresholdDropsVDDVDD0PDN0VDDCLCLPUNVDD0VDD-VTnCLVDDVDDVDD

5、VTp

6、CLSDSDVGSSSDDVGS7ComplementaryCMOSLogicStyle8ExampleGate:NAND9ExampleGate:NOR10ComplexCMOSGateOUT=D+A•(B+C

7、)DABCDABC11ConstructingaComplexGate12CellDesignStandardCellsGeneralpurposelogicCanbesynthesizedSameheight,varyingwidthDatapathCellsForregular,structureddesigns(arithmetic)IncludessomewiringinthecellFixedheightandwidth13StandardCellLayoutMethodology–1980ssignalsRoutingchannelVDDG

8、ND14StandardCellLayoutMethodology–1990sM2NoRoutingchannelsVDDGNDM3VDDGNDMirroredCellMirroredCell15StandardCellsCellboundaryNWellCellheight12metaltracksMetaltrackisapprox.3+3Pitch=repetitivedistancebetweenobjectsCellheightis“12pitch”2Rails~10InOutVDDGND16StandardCellsInOutVD

9、DGNDInOutVDDGNDWithsilicideddiffusionWithminimaldiffusionrouting17StandardCellsAOutVDDGNDB2-inputNANDgate18StickDiagramsContainsnodimensionsRepresentsrelativepositionsoftransistorsInOutVDDGNDInverterAOutVDDGNDBNAND219StickDiagramsCABX=C•(A+B)BACijjVDDXXiGNDABCPUNPDNABCLogicGra

10、ph20TwoVersionsofC•(A+B)XCABABCXVDDGNDVDDGND21C