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《FPGA时钟倍频分频DCM_IP CORE(源码及仿真图).docx》由会员上传分享，免费在线阅读，更多相关内容在行业资料-天天文库。
1、moduletb_test;//InputsregCLK_IN1;regRESET;//OutputswireCLK_OUT1;wireLOCKED;//InstantiatetheUnitUnderTest(UUT)s6_clockuut(.CLK_IN1(CLK_IN1),.CLK_OUT1(CLK_OUT1),.RESET(RESET),.LOCKED(LOCKED));initialbegin//InitializeInputs//RESET=0;//Wait100nsforglobalresettofinish//#1
2、00;CLK_IN1=0;//AddstimulushereRESET=1;#60RESET=0;foreverbegin#20CLK_IN1=!CLK_IN1;endendendmodule`timescale1ps/1ps(//ClockinportsinputCLK_IN1,//ClockoutportsoutputCLK_OUT1,//StatusandcontrolsignalsinputRESET,outputLOCKED);//Inputbuffering//----------------------------
3、--------IBUFGclkin1_buf(.O(clkin1),.I(CLK_IN1));//Clockingprimitive//------------------------------------//InstantiationoftheDCMprimitive//*Unusedinputsaretiedoff//*Unusedoutputsarelabeledunusedwirepsdone_unused;wirelocked_int;wire[7:0]status_int;wireclkfb;wireclk2x;
4、DCM_SP#(.CLKDV_DIVIDE(2.000),.CLKFX_DIVIDE(1),.CLKFX_MULTIPLY(4),.CLKIN_DIVIDE_BY_2("FALSE"),.CLKIN_PERIOD(20.0),.CLKOUT_PHASE_SHIFT("NONE"),.CLK_FEEDBACK("2X"),.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),.PHASE_SHIFT(0),.STARTUP_WAIT("FALSE"))dcm_sp_inst//Inputclock(.CLKIN
5、(clkin1),.CLKFB(clkfb),//Outputclocks.CLK0(),.CLK90(),.CLK180(),.CLK270(),.CLK2X(clk2x),.CLK2X180(),.CLKFX(),.CLKFX180(),.CLKDV(),//Portsfordynamicphaseshift.PSCLK(1'b0),.PSEN(1'b0),.PSINCDEC(1'b0),.PSDONE(),//Othercontrolandstatussignals.LOCKED(locked_int),.STATUS(s
6、tatus_int),.RST(RESET),//Unusedpin-tielow.DSSEN(1'b0));assignLOCKED=locked_int;//Outputbuffering//-----------------------------------assignclkfb=CLK_OUT1;BUFGclkout1_buf(.O(CLK_OUT1),.I(clk2x));endmodule
