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1、锁相环原理以及倍频/分频实现A phase-lockedloop (PLL)isaclosed-loopfrequency-controlsystembasedonthephasedifferencebetweentheinputclocksignalandthefeedbackclocksignalofacontrolledoscillator.Figure1showsasimplifiedblockdiagramofthemajorcomponentsinaPLL.ThemainblocksofthePLLaretheph
2、asefrequencydetector(PFD),chargepump,loopfilter,voltagecontrolledoscillator(VCO),andcounters,suchasafeedbackcounter(M),apre-scalecounter(N),andpost-scalecounters(C).注.锁相环是一种基于输入信号与输入信号反馈给振荡控制器的信号之间的相位差的闭环频率控制系统.图1展示了锁相环的基本原理框图。图中的PLL主要由鉴相器（PFD），电荷泵，回路滤波器，压控振荡电路（VCO）
3、,计数器（反馈技术器M，预分频技术器N，后分频C）.Figure1.BlockDiagramofaPLLPLLsinAltera® FPGAsaligntherisingedgeofthereferenceinputclocktoafeedbackclockusingthePFD.Thefallingedgesaredeterminedbytheduty-cyclespecifiedbytheuser.ThePFDdetectsthedifferenceinphaseandfrequencybetweenthereferenc
4、eclockandfeedbackclockinputsandgeneratesan“up”or“down”controlsignalbasedonwhetherthefeedbackfrequencyislaggingorleadingthereferencefrequency.These“up”or“down”controlsignalsdeterminewhethertheVCOneedstooperateatahigherorlowerfrequency,respectively.注.AlteraFPFG芯片内的PLL
5、中,在每个参考时钟的上升沿将通过鉴相器(PFD)产生一个反馈时钟信号.由用户指定的占空比来决定时钟的下降沿.PFD检测参考时钟与反馈时钟之间的频率差以及相位差并产生”up”或”down”的控制信号.这个控制信号表征着反馈信号是超前还是落后于参考时钟信号.这两种不同的信号决定着压控振荡器(VCO)是否需要提高频率或者降低频率.ThePFDoutputsthese“up”and“down”signalstoachargepump.Ifthechargepumpreceivesanupsignal,currentisdrivenin
6、totheloopfilter.Conversely,ifitreceivesadownsignal,currentisdrawnfromtheloopfilter.注.PFD产生的”up”,’’down”将输出给电荷泵,如果电荷泵接收到的是”up”信号,电流将进入环路滤波.相反的将从环路滤波器中吸取电流.TheloopfilterconvertsthesesignalstoacontrolvoltagethatisusedtobiastheVCO.Basedonthecontrolvoltage,theVCOoscillat
7、esatahigherorlowerfrequency,whichaffectsthephaseandfrequencyofthefeedbackclock.IfthePFDproducesanupsignal,thentheVCOfrequencyincreases.AdownsignaldecreasestheVCOfrequency.TheVCOstabilizesoncethereferenceclockandthefeedbackclockhavethesamephaseandfrequency.Theloopfil
8、terfiltersoutjitterbyremovingglitchesfromthechargepumpandpreventingvoltageover-shoot.注.环路滤波将”up””down”信号准换为压控信号传递给压控振荡器.并控制压控振荡器的振荡频率.如果PF
