sram2fifo控制器说明说

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1、Sram2fifo控制器说明书总线接口采川intel80接口进行操作：(1)Cs：片选信号，省略(2)Rs：高位命令，低位数据(3)We：数据写入使能，上升沿有效(4)Data：数据输入，16位总线实现功能用一片snun实现50M以内的读写无冲突。同时支持突发读写操作，以及任意地址的读写切换，等等等等。整个设计由同步设计，通过dcfifo异步操作，sram在百兆以内稳定可°命令解析a)单丿[sram分成了4个bank,通过命令在data[7:6J控制b)模拟突发读写操作，可通过data[5:0]调整4,8,16,32,64

2、,128,256个字节c)有待升级优化elseif(^sys_rs&sys_we)//commandbeginsram_bank<=sys_cmd[7:6];sram_rst<=11bl;case(syscmd[5:0])6'dO:length<=9'd256;6'dl:length<=91dl28;61d2:length<=9'd64;61d3:length<=9932;6'd4:length<=9'dl6;6'd5:length<=9'd8;6'd6:datalength<=9'd4;default:;endcasee

3、nddcFifo配置(1)wrfifo写fifoCurrentlyselecteddevicefamily:HowwideshouldtheFIFObe?UseadifferentoutputwidthandsettoHowdeepshouldtheFIFObe?DoyouwantacommonclockforreadingandwritingtheFIFO?Yes^synchronizebothreadingandwritingto'dock'.Createonesetoffull/emptycontrolsignals

4、.・Me.cvnrhrnnbftrAArlinnandwritinnMVdrlk'And'wrrlk'.rareqaccsasareaarequest.®Show-aheadsynchronousFIFOmode.Thedatabecomesavailablebefore'rdreq1isasserted;'rdreq1actsasareadacknowledge.Note:Thismodesuffersaperforman匚巳penalty.(1)Rdfifo读fifoCurrentlyselecteddevicefam

5、ily:HowwideshouldtheFIFObe?UseadifferentoutputwidthandsettoHowdeepshouldtheFIFObe?DoyouwantacommonclockforreadingandwritingtheFIFO?C-:*Ye勺synchronizebothreadingandwritingto上Io匚klCreateonesetoffull/emptycontrolsignals.@No丿synchronizereadingandwritingtoVddk1and'wrcl

6、k1^■JJJiwwwijyjwn■®'Show-aheadsynchronousFIFOmode.Thedatabecomesavailablebefore'rdreq1isasserted;'rdreq1actsasareadacknowledge.Note:Thismodesuffersaperformaneepenalty.操作时序图(1)Sram.rst地址清零■■■jy*xwLJL.ULJLJLILJLJLJLJULJLJLJLJULJLJLJLJULJ—/…nc_ctrl/sys」st_nStl"...ben

7、ch/sram_we_nStl卜/...fo_test/sram_addrZz・*卜hac厂hifuFnrArln卜ny—•••LUciILI1/alll—uala厶hJ…a_generate/state00Il)2:：3)：4)：5))6)7:8)9)?1卜/...enerate/data_cnt00II…nerate/delay_cnt4BtE■：av卜/...enerate/sys^data00一J...rt_top/data_validsto*...am_cmd/sram_rst0"...ifo_ctrl/wrf_

8、wrreqsto卜'...uJifo_ctrl/wrf_din00卜/...Jifo_ctrl/wrf_use00"...o_ctrl/sram_wr_acksto卜/...fifo_ctrl/sram_din00)~(0/—...o_ctrl/sram_wraddr00AiIjjIC亠亠亠亠亠亠亠亠(