VHDL数字电路设计教程第六章习题答案

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1、VHDL数字电路设计教程第六章习题答案P6.1libraryieee;useieee.std_logic_l164.all;useieee.std_logic_unsigned.all;entitychp6_lisport(clk:instd_logic;d_out:outstd_logic_vector(5downto0));end;architecturebhvofchp6_lissignalcount:std_logic_vector(5downto0);signaltemp:std_logic_vector(5downto0);beginprocess(clk

2、)beginifclk^ventandelk-Tthencount<=count+1;ifcount二T00000”thencount<=,,000000u;endif;endif;endprocess;process(clk)beginifclkreventandclk=,0,thentemp<=temp+1;iftemp=n01111ir,thentemp<=n000000n;endif;endif;endprocess;d_out<=count+temp;end;P6.3solutionllibraryieee;useieee.std_logic_lI64.al

3、l;entitychp6_3isport(x:instd_Logic_vector(7downto1);y:outstd_logic_vector(2downto0));end;architecturebhvofchp6_3isbeginprocess(x)beginifx(7)=(rtheny<=nlllu;els讦x(6)=Ttheny<=H110M;elsifx(5)=*rthenyv二T01”；elsifx(4)='1'theny<="100";elsifx(3)=Tthenyv二”011”;elsifx(2)二Ttheny<="010";elsifx(l)=

4、,rtheny<=,,001n;elsey<=,,000n;endif;endprocess;end;solution2libraryieee;useieee.std_logic_l164.all;entitychp6_3_2isgeneric(n:integer:=3);port(x:instd_logic_veclor(2**n-ldownto0);y:outintegerrange0to2**i卜1);end;architecturebhvofchp6_3_2isbeginprocess(x)variabletempintegerrange0tobeginfor

5、iinxYangeloopifx(i)=*rthentemp:=i;exit;endif;endloop;y<=temp;endprocess;end;P6.4libraryieee;useieee.std_logic_lI64.all;useieee.sld_logic_unsigned.all;entitychp6_4isgeneric(n:integer:=8);port(clk:instd_logic;clk_out:outsid」ogic);end;architecturebhvofchp6_4issignalrst:std_logic;signaltemp

6、:std_logic_vector(2downto0);beginprocess(clk,rst)beginifrst-1'thentemp<=uOOOn;elsifclk'eventandelk-Tthentemp<=temp+1;endif;endprocess;rst<='1'whentemp二”111”else'O'；clk_out<=temp(2);end;P6.5libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitychp6_5isgeneric(n:inte

7、ger:=7);port(clk:instd_logic;clk_out:outstd_logic);end;architecturebhvofchp6_5issignaltemp:stdgic_vector(2downto0);signalcout:stdgic;beginprocess(clk)beginifclkreventandelk-Tthentemp<=temp+1;iftempi110”thentemp<=n000M;endif;endif;endprocess;cout<-rwhentemp二T10”elseo；clk_out<=co