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ID:21650110
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时间:2018-10-23
《vhdl数字电路设计教程第5章习题参考答案》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、第5章习题参考答案Problem5.1libraryieee;useieee.std_logic_1164.all;packagemy_data_typeisconstantm:integer:=8;typevector_arrayisarray(naturalrange<>)ofstd_logic_vector(m-1downto0);endmy_data_type;libraryieee;useieee.std_logic_1164.all;usework.my_data_type.all;entityn_muxisgeneric(n:integer:=8);port(datain:i
2、nvector_array(0ton-1);sel:inintegerrange0ton-1;dataout:outstd_logic_vector(m-1downto0));end;architecturebhvofn_muxisbegindataout<=datain(sel);end;Problem5.2方法一:利用简单赋值语句设计libraryieee;useieee.std_logic_1164.all;entitypriority_encoderisport(x:instd_logic_vector(7downto1);y:outstd_logic_vector(2downto
3、0));end;architecturebhvofpriority_encoderisbeginy(2)<=x(7)orx(6)orx(5)orx(4);y(1)<=x(7)orx(6)or((notx(5)andnotx(4))and(x(3)orx(2)));y(0)<=x(7)or(notx(6)and(x(5)or(notx(4)and(x(3)or(notx(2)andx(1))))));end;方法二:利用WHEN语句设计libraryieee;useieee.std_logic_1164.all;entitypriority_encoderisport(x:instd_log
4、ic_vector(7downto1);y:outstd_logic_vector(2downto0));end;architecturebhvofpriority_encoderisbeginy<="111"whenx(7)='1'else"110"whenx(6)='1'else"101"whenx(5)='1'else"100"whenx(4)='1'else"011"whenx(3)='1'else"010"whenx(2)='1'else"001"whenx(1)='1'else"000";end;Problem5.4libraryieee;useieee.std_logic_1
5、164.all;useieee.std_logic_unsigned.all;entityadder8isport(a,b:instd_logic_vector(7downto0);cin:instd_logic;sum:outstd_logic_vector(7downto0);cout:outstd_logic);end;architecturebhvofadder8issignala0,b0,cin0,s:std_logic_vector(8downto0);begina0<='0'&a;b0<='0'&b;cin0<="00000000"&cin;s<=a0+b0+cin0;sum
6、<=s(7downto0);cout<=s(8);end;Problem5.5libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;useieee.std_logic_signed.all;entityadd_subisport(a,b:inunsigned(7downto0);sel:inbit_vector(1downto0);sum:outstd_logic_vector(8downto0));end;architecturebhvofadd_
7、subissignaltemp1,temp2:unsigned(8downto0);signaltemp3,temp4:signed(8downto0);--signalan,as,sn,ss:std_logic_vector(8downto0);signala0,b0:signed(7downto0);signalcin0:std_logic_vector(7downto0);begina0<=conv_signed(
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