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1、DesignofPLCTimerSystemBasedonFPGALiKejian,LiuTong,CaiQizhongSchoolofElectronicInformationandControlEngGuangxiUniversityofTechnologyLiuzhouGuangxiChinalijian6262@I26.com;srk04I26@I26.com;cqiqzh@163.comAbstract-AimingatthedesignofthesmallPLCtimersystem,base
2、dontheanalysisofoperationalcharacteristicsofPLCtimerandtheprocessofPLCusertimerprogramandthedatatransmissionrequirementsofPLCuserprogramexecutionmoduleandthetimer,amethodwhichappliestheFPGAParallelalgorithmtodesigningsmallPLCtimersystem,ispresented.Thetim
3、ersystemiscomposedofclockgeneratorunit,timingunit,timingcontrolunitandthechipselectcircuit.Whilethetimerrunsatthespeedoflmstimedpulse,theoperationoftimeristranslatedintotheoperationofRAMmemorycellwhichismadeupofFPGA.ThatmakesusercanoperateonRAMmemorycelli
4、nsteadofthetimer,anditjusttakeupafewexecutiontimeofPLCuserprogram.ThispaperintroducesthetheoryandstructureoftheFPGAtimersystem,thestatetransitiondiagramoftimercontrolmodule,thetimingdiagramofuserprogramexecutionmoduleoperatingontimer,finallytakeanexperime
5、ntandgivesanalysisoftheresults.Keywords-PLetimersystem;FPGA;dynamicin/ormationcode;paralle/operation;statetransition;1.INTRODUCTIONTimerisanimportantsoft-devicesofProgrammableLogicController(PLC)[1][2],whichisusedasthetimerelayofrelaycontrolsystem.Timeris
6、widelyusedinautomaticcontrolsystem,suchastimingsampling,timinginspection,timingscanning,etc.Theimplementationsoftimingarenon-programmablehardwaretiming,softwaretimingandprogrammablehardwaretiming.PLCprovideshundredstothousandsoftimers[3][4],andtheirtiming
7、unittypicallyhasthreekindslike1ms,10msandlOOms.Ifthetimerwereimplementedallbyhardwaredesign,itwouldberelativelysimplebutwouldtakeupalotofhardwareresources.Therefore,ithasgreatpracticalsignificancetoimplementedthislargenumberoftimerfunctionsreasonably.This
8、paperproposesatheoryusingtheFPGAParallelalgorithmtodesignasmallPLCtimersystem.Thistimersystemiscomposedofclockgeneratorunit,timingunit,timingcontrolunitandthechipselectcircuit.Eachtimingunitismadeupof3bitdynamicinfo
