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1、高风顶层模块moduletop(seg,dig,ena,ove_led,gate,dp,khz_led,elk,clk2,key1,key2,key3,reset);inputclk,clk2,kcyl,kcy2,kcy3,reset;outputena,ove_led,gate,dp,khz_led;output[6:0]seg;output[2:0]dig;wireclk_l0hz,clk_l00hz,clk_lkhz,clk_10khz,fre10,load,clr_count,ove;wire[
2、3:0Jcnt0,cnt1,cnt2,cnt3,cnt4,cnt5;divclkUl(.clk(clk),.clk_10hz(clk_10hz),.clk_100hz(clk_lOOhz),.clk_lkhz(clk_lkhz),,clk_l()khz(clk_10khz))；changU2(,clk_10hz(clk_10hz),.clk_l()()hz(clk_l(X)hz),.clk_lkhz(clk_lkhz),.clk_10khz(clk_10khz),.key1(key1),.key2(ke
3、y2),.key3(key3),.frclO(frclO))；gatetestU3(.frclO(frclO),.gate(gate),.load(load),.clr_count(clr_count))；counterU4(.clk_lkhz(clk_lkhz),.reset(reset),•clk2(clk2),.gate(gate),.clr_count(clr_count),.cntO(cntO),.ent1(ent1),.cnt2(cnt2),.cnt3(cnt3),.cnt4(cnt4),.
4、cnt5(cnt5),・ove(ove));decodeU5(.dig(dig),.1oad(load),.ena(ena),.seg(seg),.clk_lkhz(clk_lkhz),•key1(key1),.key2(key2),.key3(key3),•dp(dp),.khz_lcd(khz_lcd),.ove(ove),・ove_led(ove」ed),.cntO(cntO),.ent1(ent1),.cnt2(cnt2),>cnt3(cnt3),.cnt4(cnt4),.cnt5(cnt5))
5、;Endmodule分频器moduledivclk(clk,clk_lOhz,clk_l00hz,clk_lkhz,clk_lOkhz);inputelk;outputregclk_10hz,clk_100h乙clk_lkhz,clk_10khz;reg[29:0]counter1,counter2,counter3,counter4;initialbegincounterI<=0;counter2<=0;counter3<=0;counter4<=0;clk_10hz<=0;clk_l00hz<=0;
6、clk_lkhz<=0;clk_l0khz<=0;always@(posedgeelk)beginif(counter1==2400000)begincounter1<=0;clk_l0hz<=-clk_lOhz;endelsebegincounter1<=counter1+1;endif(countcr2==240000)begincounter2<=0;clk_100hz<=~clk_100hz;endelsebegincounter2<=counter2+1;endif(counter3==240
7、00)begincounter3<=0;clk_1khz<=-clk_1khz;endelsebegincounter3<=counter3+1;endif(counter4==2400)begincounter4<=0;clk_10khz<=^clk_10khz;endelsebegincountcr4<=countcr4+1;cndendendmodule按键换挡modulechang(clk_1Ohz,clk_100hz,clk_1khz,clk_1Okhz,key1,key2,key3,fre1
8、0);inputclk_1Ohz,clk_100hz,clk_lkhz,clk_1Okhz;inputkeyl,key2,key3;outputregfrelO;always@(posedgeclk_l()khz)beginif((key1==0)&&(key2==1)&&(key3==1))beginfre10<=clk_lOhziendelseif((key1==1)&&(key2==0)&&(key3==1))beginfro10<=
