Module 22 - Signal Integrity

Module 22 - Signal Integrity

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时间:2019-08-11

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1、Module22:SignalIntegrityModule22:SignalIntegrity22.1SignalIntegrity................................................................................22-122.2CheckingSignalIntegrityonanFPGAdesign.............................22-322.2.1SettingUp..........................................................

2、...........................................22-322.2.2ImportingIBISModels..................................................................................22-322.2.3InitialIOStandard,DriveandSlewsettings.................................................22-422.2.4SimulatingtheReflectingCharacteristic

3、s.....................................................22-622.2.5CheckingforCrosstalk...............................................................................22-1022.2.6FindingcoupledNets..................................................................................22-1122.2.7PerformingCro

4、sstalkAnalysis...................................................................22-1322.2.8SummingUp...............................................................................................22-14Software,documentationandrelatedmaterials:Copyright©2008AltiumLimited.Allrightsreserved.Youareper

5、mittedtoprintthisdocumentprovidedthat(1)theuseofsuchisforpersonaluseonlyandwillnotbecopiedorpostedonanynetworkcomputerorbroadcastinanymedia,and(2)nomodificationsofthedocumentismade.Unauthorizedduplication,inwholeorpart,ofthisdocumentbyanymeans,mechanicalorelectronic,includingtranslationintoanother

6、language,exceptforbriefexcerptsinpublishedreviews,isprohibitedwithouttheexpresswrittenpermissionofAltiumLimited.Unauthorizedduplicationofthisworkmayalsobeprohibitedbylocalstatute.Violatorsmaybesubjecttobothcriminalandcivilpenalties,includingfinesand/orimprisonment.Altium,AltiumDesigner,BoardInsigh

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