CORDIC算法VHDL实现

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1、LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;USEieee.STD_LOGIC_UNSIGNED.all;ENTITYcordicCOS_SINISPORT(clk:INstd_logic;deg_in:INstd_logic_vector(13downto0);cos:OUTstd_logic_vector(15downto0);sin:OUTstd_logic_vector(15downto0));ENDcordicCOS_SIN;architecturerlt_cordicCOS_SINo

2、fcordicCOS_SINisconstantc1:std_logic_vector(13downto0):=CONV_STD_LOGIC_VECTOR(4096,14);constantc2:std_logic_vector(13downto0):=CONV_STD_LOGIC_VECTOR(2048,14);constantc3:std_logic_vector(13downto0):=CONV_STD_LOGIC_VECTOR(1209,14);--arctan(1/2)constantc4:std_logic_vector(13downto0):=CONV_STD_LOGI

3、C_VECTOR(639,14);--arctan(1/4)--constantx0:std_logic_vector(15downto0):=CONV_STD_LOGIC_VECTOR(19895,16);signalx0:std_logic_vector(15downto0);signaly1,x1:std_logic_vector(15downto0);signaly2,x2:std_logic_vector(15downto0);signaly3,x3:std_logic_vector(17downto0);signaly4,x4:std_logic_vector(19dow

4、nto0);signalp1,p2,p3,p4:std_logic_vector(13downto0);beginx0<=conv_std_logic_vector(26980,16);---------------------------------step1------------------------------------process(clk)beginifrising_edge(clk)thenifdeg_in(13)='1'theny1<=x"0000"-x0;elsey1<=x0;endif;endif;endprocess;process(clk)beginifr

5、ising_edge(clk)thenx1<=(others=>'0');endif;endprocess;process(clk)beginifrising_edge(clk)thenifdeg_in(13)='1'thenp1<=deg_in+c1;elsep1<=deg_in-c1;endif;endif;endprocess;---------------------------------step2------------------------------------process(clk)beginifrising_edge(clk)thenifp1(13)='1'th

6、eny2<=y1-x1;elsey2<=y1+x1;endif;endif;endprocess;process(clk)beginifrising_edge(clk)thenifp1(13)='1'thenx2<=x1+y1;elsex2<=x1-y1;endif;endif;endprocess;process(clk)beginifrising_edge(clk)thenifp1(13)='1'thenp2<=p1+c2;elsep2<=p1-c2;endif;endif;endprocess;---------------------------------step3----

7、--------------------------------process(clk)beginifrising_edge(clk)thenifp2(13)='1'theny3<=(y2(15)&y2&'0')-(x2(15)&x2(15)&x2);elsey3<=(y2(15)&y2&'0')+(x2(15)&x2(15)&x2);endif;endif;endprocess;process(clk)beginifrising_edge(clk)the