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1、基本逻辑电路设计组合逻辑电路时序电路设计存储器组合逻辑电路设计简单门电路编、译码器与选择器加法器、求补器三态门及总线缓冲器简单门电路libraryIEEE;useIEEE.STD_LOGIC_1164.all;entitynand2isport(a:inSTD_LOGIC;b:inSTD_LOGIC;y:outSTD_LOGIC);endnand2;architecturenand2ofnand2isbeginy<=anandb;endnand2;&abyarchitecturenand2ofnand2isbeginprocess(a,b)variablecomb:std_lo
2、gic_vector(1downto0);comb:=a&b;casecombiswhen"00"=>y<='1';when"01"=>y<='1';when“10"=>y<='1';when“11"=>y<='0';whenothers=>y<='Z';endcase;endprocess;endnand2;或非门y<=anorb;+abycasecombiswhen"00"=>y<='1';when"01"=>y<='1';when“10"=>y<='1';when“11"=>y<='0';whenothers=>y<='Z';endcase;反相器y<=nota;ayif
3、a='1'theny<='0';elsey<='1';endif;异或门y<=axorb;+abycasecombiswhen"00"=>y<=‘0';when"01"=>y<='1';when“10"=>y<='1';when“11"=>y<='0';whenothers=>y<='Z';endcase;编码器IF(d（0）＝‘0’）THENq<=“11”;ELSIF(d(1)=‘0’)THENq<=“10”;ELSIF(d(2)=‘0’)THENq<=“01”;ELSEq<=“00”;ENDIF;d0d1y1d2d3y0译码器CaseaisWhen“000”=>q<=“11
4、111110”;When“001”=>q<=“11111101”;…..When“111”=>q<=“01111111”;Whenorthers=>q<=“ZZZZZZZZ”;Endcase;ElseQ<=“ZZZZZZZZ”;Endif;选择器ifsel="00"theny<=a;elsifsel="01"theny<=b;elsifsel="10"theny<=c;elsey<=d;endif;aby1cdy0Sel[1..0]半加器二进制输入和输出进位输出basco0011010101100001半加器真值表半加器abscolibraryIEEE;useIEEE.STD_
5、LOGIC_1164.all;entityhalf_adderisport(a:inSTD_LOGIC;b:inSTD_LOGIC;s:outSTD_LOGIC;co:outSTD_LOGIC);endhalf_adder;architecturehalf_adderofhalf_adderissignalc,d:std_logic;beginc<=aorb;d<=anandb;co<=notd;s<=candd;endhalf_adder;全加器半加器ab+co半加器cinsU0_su1u2U0_colibraryIEEE;useIEEE.STD_LOGIC_1164.all
6、;entityfull_adderisport(a,b,cin:inSTD_LOGIC;co,s:outSTD_LOGIC);endfull_adder;architecturefull_adderoffull_adderiscomponenthalf_adderport(a,b:inSTD_LOGIC;s,co:outSTD_LOGIC);endcomponent;signalu0_co,u0_s,u1_co:std_logic;beginu0:half_adderportmap(a,b,u0_s,u0_co);u1:half_adderportmap(u0_s,b,cin,
7、s,u1_co);co<=u0_cooru1_co;endfull_adder;三态门ifen='1'thendout<=din;elsedout<='Z';endif;单向总线缓冲器ifen='1'thendout<=din;elsedout<=“ZZZZZZZZ”;endif;双向缓冲器缓冲器adrbenendr功能00a=b01b=a1X三态双向总线缓冲器真值表process(a,dr,en)beginifen='0'anddr='1'thenbout<=a;elsebout<="ZZ
