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ID:58637052
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页数:11页
时间:2020-10-17
《EDA中VHDL基本逻辑电路设计.docx》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、第三章基本逻辑电路设计3.1组合逻辑电路设计一、简单门电路设计例:3输入“与非”门电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnand3ISPORT(a,b,c:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnand3;ARCHITECTUREnand3_1OFnand3ISBEGINy<=NOT(aANDbANDc);ENDnand3_1;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnand3ISPORT(a,b,c:INSTD_LOGIC;y:OUTSTD_
2、LOGIC);ENDnand3;ARCHITECTUREnand3_2OFnand3ISBEGINt4:PROCESS(a,b,c)VARIABLEcomb:STD_LOGIC_VECTOR(2DOWNTO0);BEGINcomb:=a&b&c;CASEcombISWHEN“000”=>y<=‘1’;WHEN“001”=>y<=‘1’;WHEN“010”=>y<=‘1’;WHEN“011”=>y<=‘1’;WHEN“100”=>y<=‘1’;WHEN“101”=>y<=‘1’;WHEN“110”=>y<=‘1’;WHEN“111”=>y<=‘0’;WHENOTHERS=>
3、y<=‘X’;ENDCASE;ENDPROCESS;ENDnand3_2;二、编码器、译码器、选择器例:地址译码器假设一个微处理器存储空间为从0000H到FFFFH,将其分成5部分,它们的地址分配如下:0000H—DFFFH为动态随机存储器DRAM使用;E000H—E7FFH为I/O设备使用;E800H---EFFFH备用;F000H—F7FFH为第一个只读存储器ROM1使用;F800H—FFFFH为第二个只读存储器ROM2使用;其中选通控制信号DRAM1,IO,ROM1,ROM2均为低电平有效。例:地址全译码LIBRARYIEEE;USEIEEE.STD_LOGIC_1
4、164.ALL;ENTITYad_decoderISPORT(address:INSTD_LOGIC_VECTOR(15downto0);DRAM1,IO,ROM1,ROM2:OUTSTD_LOGIC);ENDad_decoder;ARCHITECTUREaOFad_decoderISBEGINPROCESS(address)BEGINIFaddress<=x”dfff”THENDRAM<=‘0’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘1’;ELSIFaddress>=x”e000”ANDaddress<=x”e7ff”THENDRAM<=‘1’;IO<=‘0
5、’;ROM1<=‘1’;ROM2<=‘1’;ELSIFaddress>=x”f000”ANDaddress<=x”f7ff”THENDRAM<=‘1’;IO<=‘1’;ROM1<=‘0’;ROM2<=‘1’;ELSIFaddress>=x”f800”THENDRAM<=‘1’;I/O<=‘1’;ROM1<=‘1’;ROM2<=‘0’;ENDIF;EndPROCESS;ENDa;例:地址部分译码LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYad_decoderISPORT(A15,A14,A13,A12,A11:INSTD_LOG
6、IC;DRAM1,IO,ROM1,ROM2:OUTSTD_LOGIC);ENDad_decoder;ARCHITECTUREaOFad_decoderISBEGINPROCESS(A15,A14,A13,A12,A11)BEGINIF(A15ANDA14ANDA13)=‘0’THENDRAM<=‘0’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘1’;ELSIFA12=‘0’ANDA11=‘0’THENDRAM<=‘1’;IO<=‘0’;ROM1<=‘1’;ROM2<=‘1’;ELSIFA12=‘1’ANDA11=‘0’THENDRAM<=‘1’;IO<=‘1’;R
7、OM1<=‘0’;ROM2<=‘1’;ELSIFA12=‘1’ANDA11=‘1’THENDRAM<=‘1’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘0’;ENDIF;ENDPROCESS;ENDa;三、加法器、求补器例:半加器真值表二进制输入和输出进位输出basco0011010101100001例:8位二进制数的求补电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhalf_adderISPORT(a,b:INSTD_LOGIC;s,co:OUTSTD_LOGIC);E
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