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1、Cadence后端实验系列19_版图验证_AssuraIntroductiontoAssuraPhysicalVerificationAssuraPhysicalVerificationToolSuiteAssuraTaskandDataFlowAssuraInputFilesRunningAssuraDRCGraphicalUserInterfaceRunGuideLVSGraphicalUserInterfaceRunGuideRCXGraphicalUserInterfaceRunGuideDemonstrationOUTLINEIntroductionto
2、AssuraPhysicalVerificationAssuraPhysicalVerificationToolSuiteAssuraTaskandDataFlowAssuraInputFilesRunningAssuraDRCGraphicalUserInterfaceRunGuideLVSGraphicalUserInterfaceRunGuideRCXGraphicalUserInterfaceRunGuideDemonstrationOUTLINEAssuraPhysicalVerificationToolSuiteTheAssuraverification
3、suiteisoptimizedforlarge,hierarchical,repetitivedesignssuchasmemory,microprocessor,andmixed-signalcircuits.ThesoftwareupholdstheCadenceverificationtraditionofaccuracyestablishedbyitsDracula®andDiva®products.TheAssuratoolsensureaccuracyandleveragethelayouthierarchyofleading-edgedesigns
4、toprovidefasterphysicalverificationruntimes.AssuraPhysicalVerificationToolSuiteAssuraDRC–AssuraDRC(DesignRuleChecking)checksthelayoutagainstgeometricspacing,width,andotherrules.Typicalchecksincludematerialspacing,enclosure,coverage,andoverlap.AssuraDRCdisplaysdesignruleviolationsgraph
5、icallyasanadditionalgraphicslayeronthelayout,andliststhemintextfiles.AssuraLVS–AssuraLVS(LayoutVersusSchematic)comparisonextractsdevicesandconnectivityfromthelayoutaccordingtodeviceextractionrules,thencreatesalayoutnetlistaccordingtonetlistrules,thenfinallycomparesthelayoutnetlisttothe
6、schematicnetlistaccordingtocomparisonrules.AssuraLVSdisplaysmismatchesbetweenthelayoutandtheschematicbothtextuallyandgraphically.AssuraRCX–AssuraRCX(Resistance,CapacitanceandInductanceExtraction)extractsparasiticresistance,capacitance,andinductancefromthelayoutforanalysisandinputtopo
7、st-layoutsimulators.AssuraTaskandDataFlowAssuraInputFilesSchematicNetlistsLayoutGeometryDataRun-SpecificFile(RSF)RuleFileRun-SpecificFile(RSF)TheAssuraRSFisarequiredcontrolfileintextformatthatdirectstheAssuraDRC,LVS,orRCXrun.Itspecifiesinputdatafiles,rulefiles,run-specificoptions,andcommand
8、stoinvokethe
