DDR3 Power Integrity

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1、DDR3PowerIntegritySolutionsSanDiskInternalWorkshop2012BenChiaSignalIntegrityConsultant7/18/2012Overview•Powernoisebecomesmajornoisebudgetforhighspeedsystem•Lowcostpackageandlowpowercircuitrequirescleanerpowerdelivery•Powernoiseproblemcanbeexpensivetofixatthelatecycleofproductdevelopment•Powe

2、rintegritydesignaffectson-chip,packageandPCBHighSpeedDC.comSlide2Outline•SectionI•Introducingbasicpowerdeliveryissue•Powerdeliverynetworkimpedance•Modelingandsimulation•SectionII•Powerintegritydesignmethodology•TimingmarginHighSpeedDC.comSlide3PowerIntegrityProblem•VoltageatASIC•Mustbeheldto

3、within5-10%tolerance•CurrentatASIC•Draw10Aormoreperchip,100Aperboard•Currentmaygofrom0tofullcurrentinlessthanoneclockcycle•Powersupplynetwork•PCBpowerplane,package,bondwire,on-chipresistanceandcapacitanceHowtoensurethepowerstayswithinthe5%ofspecification?HighSpeedDC.comSlide4CurrentChangeatD

4、ifferentRate•Processorwakesupin0.2clockcycle•Memoryoperationstartsin5clockcycle•Memoryread/writeturn-aroundoperationin2cycles•Powersupplycannotprovideenergyfastenough,whatisthereason?VoltageRegulator50A/uSec–tooslowHighSpeedDC.comSlide5Thefundamental-inductance•Inductanceactsasopencircuitath

5、ighfrequency•CurrentcannotflowthroughinductancefastenoughtoprovideenergytothecircuitintimeIVoLV,IVoRRVRMSolution:addparallelcapacitorsclosetoneedycircuitHighSpeedDC.comSlide6AnotherFundamental•Howfastthecircuitneedsenergy?•DeterminedbyIntel/Altera..Specification•CircuitOperationsdeterminete

6、stpatterns•Systemwakeupfromsleepmode•Memorytransaction•IdleReadIdleWrite•IdleReadWrite•IdleDRAMRefresh•IOactivities•Testpatternfrequency≠SystemresonancefrequencyWhatissystemresonancefrequency?HighSpeedDC.comSlide7LCResonantCircuit•ParallelResonance•opencircuit•Example:ASICandbypasscapa

7、citor•Serialresonance•Shortcircuit•BypassCapacitorWhatistheworstresonancefrequencyinpowerntwk?HighSpeedDC.comSlide8TypicalPowerDeliverySystemHighSpeedDC.comSlide9Outline•Powernetworkimpedanceconcept•VoltageSource–VoltageRegulatorModule(VRM)•Measure