Buffer flip-flop block planning for power-integrity-driven floorplanning.pdf

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1、Buffer/Flip-FlopBlockPlanningforPower-Integrity-DrivenFloorplanningHsin-HuaPan1,Hung-MingChen2,andChia-YiChang31AnaGlobeTechnology,Inc.,HsinchuScience-BasedIndustrialPark,Hsinchu,Taiwan2DepartmentofElectronicsEngineering,NationalChiaoTungUniversity,Hsinchu,Taiwan3RealtekSemiconductorCorp.,Scien

2、ce-BasedIndustrialPark,Hsinchu,TaiwanAbstract—Asthetechnologyscaleddown,itisknownthatinterconnecthasbecomethedominantfactorindeterminingtheoverallcircuitperformanceandcomplexity.Bufferinsertionisoneofveryeffectiveandusefultechniquestoimprovetheinter-connectperformance.Inordertofindbetterplacesfo

3、rbufferstobeinserted,thebufferinsertionstageduringfloorplanningusuallyclustersbuffersinaregion,whichmaycauseadditionalIR-dropviolation.Ontheotherhand,incomplexdigitalsystemwithrelativelylargedieareasoperatingatveryhighfrequencies,manyglobalsignalstravelingacrossthechipneedseveralclockcyclestorea

4、chtheirdestinations,thusrequiringtheadoptionofpipelinedinterconnects.Togetherwiththebufferstations/blocks,theincreasingnumberofflip-flopswillcausefurthervoltagedropFig.1.Left-handsideofthefigureshowsaninstanceoffloorplananditsviolation.Inthispaper,weproposeamethodologytopipelineP/Gnetworkstructure.

5、Theworst-voltageattheP/Gpinsisabout5%ofinterconnectduringthefloorplanstageandconsidertheIR-dropthesupplyvoltage[15].Right-handsideoffigureshowsthatafterthebufferduringtheplanningofbuffersandflip-flopsatthesametime.Theinsertion,theworse-casevoltagedropisincreasedfrom5%to5.6%.experimentalresultsshowt

6、hatourmethodcangetalowsystemlatencywithpowerintegritypreservationin90nmtechnologynode.networkconstruction[21].Foragivenfloorplan,channelsanddeadspacesareusedasbufferblocks,whichaccommodateI.Introductionbuffers[9][17][18].Ifagivenfloorplanisnotgoodenough,theFordeepsubmicron(DSM)andnanometerVLSIdes

7、igns,itexpansioncausedbytheinsertionofbufferswouldresultiniswidelyacceptedthatinterconnecthasbecomethedominantmoreareaoverhead.[11]integratedthebufferblockplanningfactorindeterminingtheoverallcircuitperformanceandintofloorplannings