Study of Signal and Power Integrity Challenges in High Speed Memory IO Designs Using Single-Ended Siganling Schemes

Study of Signal and Power Integrity Challenges in High Speed Memory IO Designs Using Single-Ended Siganling Schemes

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时间:2019-07-16

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1、DesignCon2008StudyofSignalandPowerIntegrityChallengesinHigh-SpeedMemoryI/ODesignsUsingSingle-EndedSignalingSchemesDanOh,RambusInc.[doh@rambus.com]WoopoungKim,RambusInc.Joong-HoKim,RambusInc.JohnWilson,RambusInc.RalfSchmitt,RambusInc.ChuckYuan,RambusInc.LeiLuo,RambusInc

2、.JadeKizer,RambusInc.JohnEble,RambusInc.FredWare,RambusInc.AbstractIncontrasttomostchip-to-chipI/Ointerfacesthatusedifferentialsignaling,themainstreammemoryinterfacedesignsarebasedonsingle-endedsignalingsuchasSSTLorPODL.Extendingthedatarateforsingle-endedsignalingbeyon

3、dcurrentdatarateofafewGb/sisbecomingverydifficult.Thispaperstudiestheimpactofvarioussignalandpowernoisecomponentsonthepotentialdatarateofsingle-endedsignalingsystems.Althoughourdiscussioncoversgeneralsingle-endedsignalingsystems,GDDR3/4memorysystemsareconsideredasdetai

4、ledexamples.Inparticular,theperformanceofvariouspackages,motherboards,codingschemes,andequalizationtechniquesareevaluated.Weshowthatthecrosstalkimpactcanbemitigatedbyemployingstriplinedesigns,incurringhighcostinsystemdesign.However,thepotentialdatarateisstilllimitedbyS

5、SOnoise.TheDBIcodingtechniquerecentlyintroducedinGDDR4reducesSSOnoisesignificantlybutthefinalsystemperformancegainismarginalafteraccountingforthepinoverhead.Finally,arelativeperformancegainusingvariousdifferentsingle-endedsignalingoptionsisgivenandcomparedwithanequival

6、entdifferentialsystem.Author(s)BiographyKyungSuk(Dan)OhisSeniorEngineeringManageratRambusInc.HereceivedhisB.S.,M.S.,andPh.D.inelectricalengineeringfromtheUniversityofIllinois,atUrbana-Champaignin1990,1992,and1995,respectively.Hisdoctoralresearchwasintheareaofcomputatio

7、nalelectromagneticsappliedtotransmissionlinemodelingandsimulation.Since2000,heiswithRambusInc.,LosAltos,CA.Hisgroupisresponsibleforprovidingsignalintegrityanalysisforvariousproductsincludingserial,parallel,andmemoryinterfaces.Additionalresponsibilitiesofhisgroupinclude

8、anadvanceCADtooldevelopmentforhigh-speedlinksimulation.Hiscurrentinterestsincludeadvancesignalandpowerintegritymodeli

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