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1、A1.9mWPortableADPLL-basedFrequencySynthesizerforHighSpeedClockGenerationMing-HungChang,StudentMember,IEEE,Zong-XiYang,andWeiHwang,Fellow,IEEEDepartmentofElectronicsEngineering&InstituteofElectronics,MicroelectronicsandInformationSystemResearchCenter(MIRC),NationalChiao-TungUn
2、iversity,Hsin-Chu300,TaiwanAbstract—AnADPLL-basedfrequencysynthesizerhasbeendesignedandimplementedwithTSMC130nmtechnologymodel.Thecoresofitaredigitalcontrolledoscillator(DCO)andphasefrequencydetector(PFD).Amodifieddigitallycontrolleddelayelement(DCDE)withcharacteristicsofitsm
3、onotonicityandinsensitivitytoPVTvariationsispresentedfortheDCOdesign.AnewPFDarchitecturethatcanfinishphaseandfrequencycomparisonandadjustmentinonereferencecycleispresented.Thisfrequencysynthesizercanoperatefrom300MHzto1GHz,andachievefrequencyacquisitioninfifteenreferenceclock
4、cycles(worstcasescenario).Thepeak-to-peakjitteroftheoutputclockislessthan120psat300MHz.Furthermore,thedesignhasbeenFigure1.ADPLL-basedfrequencysynthesizerblockdiagram.portedtoTSMC100nmprocessasareusableIPblockverification.ThetotalpowerdissipationoftheADPLL-basedfrequencysynth
5、esizeris1.9mW(TSMC100nmtechnology)at1GHzwitha1.2Vpowersupply.Withsuchspecifications,itissuitableforhighspeedclockgenerationinsystem-on-a-chip(SoC)applications.I.INTRODUCTIONThephase-lockedloop(PLL)hasbeendesignedforapplicationandintegrationonhighspeedmicroprocessors.Figure2.M
6、odifiedbinarysearchalgorithm.Intraditionalmixed-signalsystem,PLLisusuallylayoutthatsubstantiallydecreasethedesigncycleefficiency.implementedbyanalogbuildingblock.However,owingtoNotonlyportabilitybutalsoarea-effectivelow-powerdesirablecharacteristicsrelatingtosystemintegration
7、incapabilitywouldbeemphasizedinthispaper.state-of-the-artcomplexSoCenvironment,alldigitalphase-lockedloop(ADPLL)iscurrentlychosenforsystemTherestofthispaperisorganizedasfollows:SectionIIfrequencysynthesisapplications.Notonlyinsensibilitytodescribesthearchitectureandlockproced
8、ureoftheADPLL.processvariationsbutalsoportabilitytoeachnewThepropose
