实验九 任意编码计数器的设计

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1、实验九任意编码计数器的设计一、实验目的1、通过任意编码计数器体会语言编程设计电路的便利。2、了解状态机的设计原理。二、实验内容用状态机设计任意编码计数器，实现如下编码7进制计数器：0，2，5，3，4，6，1，并通过数码管显示。三、实验原理状态转移图四、引脚分配情况：下表为GX-SOC/SOPC-EP2C35-M672创新开发实验平台引脚分配建议表设计端口芯片引脚开发平台模块out[0]AE13HEX_1Aout[1]AF13HEX_1Bout[2]AD12HEX_1Cout[3]AE12HEX_1Dout[4]AA12H

2、EX_1Eout[5]Y12HEX_1Fout[6]V11HEX_1GclkP2550M主时钟rstF6SW1A五、实验报告要求实验报告上要体现系统的设计过程，包括所有的代码、仿真结果和硬件验证结果。libraryIEEE;---get1HZuseIEEE.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydividefisport(CLK:instd_logic;CLK_D:outstd_logic);endentity;architectureDIVIDE

3、_archofdividefissignalCOUNT:integerrange0to50000000;beginPROCESS(CLK)BEGINifclk'eventandclk='1'thenIFCOUNT=50000000thenCOUNT<=0;ELSECOUNT<=count+1;ENDIF;ENDIF;ENDPROCESS;PROCESS(COUNT)BEGINIFCOUNT=50000000THENCLK_D<='1';ELSECLK_D<='0';ENDIF;ENDPROCESS;endarchitec

4、ture;libraryieee;useieee.std_logic_1164.all;entityxsb1isport(clk:instd_logic;reset:instd_logic;d:outstd_logic_vector(2downto0));endxsb1;architecturexsb1_archofxsb1istypestateis(s1,s2,s3,s4,s5,s6,s7);signalnext_state,current_state:state;beginprocess(reset,current_

5、state)begincasecurrent_stateiswhens1=>d<="000";ifreset='1'thennext_state<=s1;elsenext_state<=s2;endif;whens2=>d<="010";ifreset='1'thennext_state<=s1;elsenext_state<=s3;endif;whens3=>d<="101";ifreset='1'thennext_state<=s1;elsenext_state<=s4;endif;whens4=>d<="011";

6、ifreset='1'thennext_state<=s1;elsenext_state<=s5;endif;whens5=>d<="100";ifreset='1'thennext_state<=s1;elsenext_state<=s6;endif;whens6=>d<="110";ifreset='1'thennext_state<=s1;elsenext_state<=s7;endif;whens7=>d<="001";ifreset='1'thennext_state<=s1;elsenext_state<=s

7、2;endif;endcase;endprocess;process(clk)beginifclk='1'andclk'eventthencurrent_state<=next_state;endif;endprocess;endxsb1_arch;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityseg7isport(indata:instd_logic_vect

8、or(3downto0);outdata:outstd_logic_vector(0to6));endseg7;architecturebehaviorofseg7isbeginwithindataselectoutdata<="1111110"when"0000","0110000"when"0001","1101