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1、IEEETRANSACTIONSONCIRCUITSANDSYSTEMSII:EXPRESSBRIEFS,VOL.57,NO.8,AUGUST2010607DesignandExperimentalVerificationofaPowerEffectiveFlash-SARSubrangingADCU-FatChio,StudentMember,IEEE,He-GongWei,StudentMember,IEEE,YanZhu,StudentMember,IEEE,Sai-WengSin,Member,IEEE,Seng-PanU,SeniorMem
2、ber,IEEE,R.P.Martins,Fellow,IEEE,andFrancoMaloberti,Fellow,IEEEAbstractThisbriefpresentsthearchitecturalconceptofanTheoptimumspeedofSARconvertersiscontrolledbytheoptimalsubrangingADC,obtainedwiththecascadeofaFlashsingle-bittimeconversionthatforagiventechnologyandres-andaSAR,wh
3、ichisalsoexploredthroughitspracticaldesignolution,achievesmaximumpowereffectiveness.Forexample,andexperimentalconfirmation.Thesolutiondoublestheoptimalthe90-nmCMOStechnologypermitsthedesignof9-bitSARspeedofoperationoftheSARADCsattherelativelowpowerwith50MHzconversionspeed[5].Ab
4、ovethatlimit,itwouldcostofalow-resolutionFlash.Thedigitalcorrectionmethodandacapacitor-basedDACensurenondemandingrequirementsforbenecessarytousemoreingeniouscircuitschemes.theFlash.TheeffectivenessofthearchitectureisverifiedinaTheFlashconverterisnormallyviewedasapowerhungry90-n
5、mCMOSchipwhoseactivecoreareais0.64mm2.TheADCsolutionbecauseitrequiresanumberofcomparatorsthatobtainsapeakSNDRof51.8dBandSFDRof63.4dBat90MS/sincreaseexponentiallywiththenumberofbits.However,theconsuming13.5mWfroma0.9-Vsupply.MeasuredDNLandINLpowerconsumedbycomparatorsisonlylarg
6、eatveryhighare0.87LSBand1.55LSB,respectively.speedandhighresolution.Formediumresolution(e.g.,5-bit),IndexTermsAnalog-to-digitalconverter(ADC),digitalerrorthepowerrequestedisrelativelylowifthespeedisnotverycorrection(DEC),FlashADC,SARADC,subrangingADC.high;consequently,preampli
7、fiersdonotneedalargegain.ThisbriefverifiesonsiliconwithexperimentalresultsaI.INTRODUCTIONpowereffectivesubrangingADCarchitecturethatusesa5-bitFlashasthefirststageanda5-bitSARasthesecondstage.HEFASTshrinkingofCMOSprocesstechnologiesin-Digitalerrorcorrection(DEC)bringstheresolution
8、to9-bit.Tcreasessiliconcapacity,diminishessupplyvoltage,allow
