Verilog数字系统设计

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1、数字系统设计(Verilog)--Verilog基本语法1主要内容模块结构；数据类型；变量；基本运算符号；与C语言的比较HierarchicalDesignTopLevelModuleSub-Module1Sub-Module2BasicModule3BasicModule2BasicModule1FullAdderHalfAdderHalfAdderE.g.Modulefin1in2inNout1out2outMmy_modulemodulemy_module(out1,..,inN);outputout1,..,outM;in

2、putin1,..,inN;..//declarations..//descriptionoff(maybe..//sequential)endmodule模块结构由关键词：Moduleendmodule定义模块结构例1：D触发器moduledff_pos(data,clk,q)inputdata,clk;outputq;regq;always@(posedgeclk)q=data;endmoduleCasesensitivitymyidMyid模块引用moduletop(D,CLK,Q)inputD,CLK;OutputQ;r

3、egQ;dff_posDFF1(.data(D),.clk(CLK),.q(Q)dff_posDFF2(.data(D),…..….endmoduleExample:HalfAddermodulehalf_adder(S,C,A,B);outputS,C;inputA,B;wireS,C,A,B;assignS=A^B;assignC=A&B;endmoduleHalfAdderABSCABSCExample:FullAddermodulefull_adder(sum,cout,in1,in2,cin);outputsum,cou

4、t;inputin1,in2,cin;wiresum,cout,in1,in2,cin;wireI1,I2,I3;half_adderha1(I1,I2,in1,in2);half_adderha2(sum,I3,I1,cin);assigncout=I2

5、

6、I3;endmoduleInstancenameModulenameHalfAdderha2ABSCHalfAdder1ha1ABSCin1in2cincoutsumI1I2I3HierarchicalNamesha2.ARemembertouseinstancenames,

7、notmodulenamesHalfAdderha2ABSCHalfAdder1ha1ABSCin1in2cincoutsumI1I2I3模块内部信号说明regwirewiresigned[PhaseWidth+5:0]SignPhaseError;regsigned[PhaseWidth+5:0]SignPhaseError_d;assignSignPhaseError=in_Dir?(-in_PE):in_PE;always@(posedgein_UpdateClk)beginif(in_ResetFilter)SignPha

8、seError_d<=0;elseSignPhaseError_d<=SignPhaseError;end连续赋值语句、过程块、实例引用三项是顺序执行，但是always内的语句是顺序执行的。基本词法命名注释逻辑状态数字数据命名规则从以下符号中任意组合{[A-Z],[a-z],[0-9],_,$},但是不能以$或者[0-9]数字开头myidentifierm_y_identifier3my_identifier$my_identifier_myidentifier$CasesensitivitymyidMyid注释行与C

9、语言完全一致//Therestofthelineisacomment/*Multiplelinecomment*//*Nesting/*comments*/doNOTwork*/四种逻辑状态0representslowlogiclevelorfalsecondition1representshighlogiclevelortrueconditionxrepresentsunknownlogiclevel（不定态）zrepresentshighimpedancelogiclevel（高阻态）数字(i)’

10、alue>8’hax=1010xxxx12’o3zx7=011zzzxxx111NoofbitsBinaryborBOctaloorODecimaldorDHexadecimalhorHConsecutivechars0-f,x,z数字(i