Quartus错误大全

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1、Quartus常见错误分析1Warning:VHDLProcessStatementwarningatrandom.vhd(18):signalresetisinstatement,butisnotinsensitivitylist----没把singal放到process（）中2Warning:Foundpinsingasundefinedclocksand/ormemoryenablesInfo:AssumingnodeCLKisanundefinedclock-=-----可能是说设计中产生的触发器没有使能端3Err

2、or:VHDLInterfaceDeclarationerrorinclk_gen.vhd(29):interfaceobject"clk_scan"ofmodeoutcannotberead.Changeobjectmodetobufferorinout.------信号类型设置不对，out当作buffer来定义4Error:Nodeinstance"clk_gen1"instantiatesundefinedentity"clk_gen"-------引用的例化元件未定义实体－－entity"clk_gen"5Warn

3、ing:Found2node(s)inclockpathswhichmaybeactingasrippleand/orgatedclocks--node(s)analyzedasbuffer(s)resultinginclockskewInfo:Detectedrippleclock"clk_gen:clk_gen1/clk_incr"asbufferInfo:Detectedrippleclock"clk_gen:clk_gen1/clk_scan"asbuffer6Warning:VHDLProcessStatemen

4、twarningatledmux.vhd(15):signalorvariable"dataout"maynotbeassignedanewineverypossiblepaththroughtheProcessStatement.Signalorvariable"dataout"holdsitspreviousineverypathwithnonewassignment,whichmaycreateacombinationalloopinthecurrentdesign.7Warning:VHDLProcessState

5、mentwarningatdivider_10.vhd(17):signal"cnt"isreadinsidetheProcessStatementbutisn''tintheProcessStatement''ssensivititylist-----缺少敏感信号8Warning:Noclocktransitionon"counter_bcd7:counter_counter_clk/q_sig[3]"register9Warning:Reducedregister"counter_bcd7:counter_counte

6、r_clk/q_sig[3]"withstuckclockporttostuckGND10Warning:Circuitmaynotoperate.Detected1non-operationalpath(s)clockedbyclock"class[1]"withclockskewlargerthandatadelay.SeeCompilationReportfordetails.11Warning:Circuitmaynotoperate.Detected1non-operationalpath(s)clockedby

7、clock"sign"withclockskewlargerthandatadelay.SeeCompilationReportfordetails.12Error:VHDLerroratcounter_clk.vhd(90):actualport"class"ofmode"in"cannotbeassociatedwithformalport"class"ofmode"out"------两者不能连接起来13Warning:Ignorednodeinvectorsourcefile.Can''tfindcorrespon

8、dingnodename"class_sig[2]"indesign.------没有编写testbench文件，或者没有编辑输入变量的值testbench里是元件申明和映射14Error:VHDLBindingIndicationerroratfreqdetect_top.vhd(19):port"c