DC脚本及解释

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1、#scriptforDesignCompiler#Language:TCL#Usage:#1)makesurethelibinthecurrentdirectory#2)ifyou...#scriptforDesignCompiler#Language :TCL#Usage    :#          1)makesurethelibinthecurrentdirectory#          2)ifyouhavethefile.synopsys_dc.setup,#             setsynopsys_dc_setup_file1

2、,#             ifnot,setsynopsys_dc_setup_file0#          3)changeStep3:Variablestowhatyouwant#             Especially:topmodulename,clockname,#             resetname,allfilesname,andperiod#          4)typingdc_shell-t-frun_72.tcl

3、tee-irun.log# #================================

4、========================setsynopsys_dc_setup_file0#-----------------------------------------------------#Step1:#SettingUppathandlibrary：#Ifyouhaveeditedthefile.synopsys_dc.setup,thenyoucanskipoverthisstep#-----------------------------------------------------if{$synopsys_dc_setu

5、p_file==0}{setsearch_path[list/home/chanshi/dc/library/smic/home/chanshi/dc/rfid/source/home/chanshi/dc/script]settarget_library {typical.db}#settarget_library {CSM35OS142_typ.db};#ifyouwantusetypicallibrary,changetotypical.db#setlink_library [list{*}ram_interp_typical_syn.dbra

6、m_458_typical_syn.dbtypical.db]setlink_library [list{*}$target_library]}#setsymbol_library {csm18ic.sdbcsm18io.sdb}#setsynthetic_library {dw_foundation.sldb};#DesignWaresetcommand_log_file  "command.log"#-----------------------------------------------------#Step2:#CompileSwithe

7、s#-----------------------------------------------------#setverilogout_no_tri                 true;#ifinoutused,trinetwillbeused#通过将三态（tri）逻辑声明成线网（wire）来确保网表中不会出现三态逻辑，因为一些布线工具很难读取包含tri、tran源语、assign语句的网表，对于“inout”类型的port,DC产生triwire语句和tran源语，对于tri，还会产生assign语句settest_default_sca

8、n_style         multiplexed_flip_flop#设置扫描链的类型，还可以通过set_scan_configuration-style来设置setlink_force_case                 case_insensitive#设置link命令是否区分大小写，默认是check_reference,就是根据产生reference的模块格式来判断是否大小写敏感，如果是vhdl格式就是不敏感，如果是verilog就敏感define_name_rulesVLSI_NET-allowed"a-zA-Z0-9_"-fir

9、st_restricted"0-9_"-typenet-max_length256define_name_r