边界测试原理与应用

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1、BoundaryScanOverview「邊界掃描測試」測試原理與應用IntelligentBoundaryScanSolutions®BoundaryScanTest測試之定義所謂邊界(Boundary):係指IC腳端與內部(功能邏輯閘)晶片間之接點。換言之進行掃描測試IC腳端與晶片間之接點邊界，係所謂之「邊界掃描測試」。1990年經由IEEE1149.1加以規格化之BST測試，俗稱為「邊界掃描測試」(BoundaryScanTest)BScanBasicsMoreDetailsonIEEE-1149.1=>

2、digitalinterconnectiontest•IEEE-1149.4=>mixed-signalandanaloginterconnectiontestIEEE-1149.5=>systemleveltestIEEE-1149.6=>Differential&ACcouplednetworksIEEE-1532=>In-System-Programming7/16/20213HistoryoftheStandard1985–JETAG(JointEuropeanTestActionGroup)1986–

3、JTAG(EuropeandNorthAmerica)1988–P1149JTAGv2(proposal)1990–IEEEStd1149.1-19901993–IEEEStd1149.1a-19931994–IEEEStd1149.1b-1994(BSDL)2001–IEEEStd1149.1-2001TermssynonymswithIEEEStd1149.1BoundaryScan/BSCAN/BSTJTAG(JointTestActionGroup)7/16/20214BoundaryScanTest測

4、試之必要性BScanBasicsBoundaryScanTest測試之原理(二)若PCB印刷基板採用BScan測試相容元件時，最多僅需5條(通常為4條)之專用線，即可測試:1.TestDataIn(TDI)2.TestDataOut(TDO)3.TestModeSelect(TMS)4.TestClock(TCK)5.TestReset(TRST)=>可以省略不用*註=>通常用六個Clock，當作一個ResetBScanBasicsBoundaryScanTest測試之原理(三)所謂[測試存取埠]:TAP(Te

5、stAccessPort)=>係指為進行測試邏輯電路之指令，測試數據或測試結果等數據加入輸入/輸出之串列介面，上述4條信號線，經由外界之電腦主機加以控制，以便執行BScan測試。BScanBasicsBoundaryScanTest測試之功能<1>元件之誤插接及臨近元件的短路測試<2>外界電路與元件間之輸入/輸出信號監視<3>元件間之互接測試(InterconnectingTest)<4>可測試BGA元件之開路與短路作測試<5>Non-BGAIC腳的開路測試<6>可在板上燒錄資料(ISP)Flash/EEPRO

6、M(ISP)PLD/FPGADevices<7>內部邏輯電路之功能測試BScanBasicsTestbusSignalsTMS=TestModeSelectTCK=TestClockTDI=TestDataInTDO=TestDataOutTMSTCKTDOTAPTAPTAPBScan-deviceBScan-deviceBScan-deviceTDITestbusinterconnectionnonBScanICBScannetsIEEE-1149.1BscanCell測試存取埠TAP=TestAccessP

7、ort7/16/20219StandardDeviceCoreLogicPinIEEE-1149.17/16/202110BScanDeviceTestDataOut(TDO)TCKCoreLogicTestAccessPort(TAP)TestModeSelect(TMS)TestDataIn(TDI)TestClock(TCK)...someextra“intelligence”isneededforTestAccessBScanCellPinIEEE-1149.17/16/202111TestAccess

8、Port(TAP)測試存取埠TAPControllerInstructionsRegisterTDOTMSTDITCKBypassRegisterIDcodeRegister,opt.BScanRegister310n000nMUXDataRegisterIEEE-1149.17/16/202112IEEE-1532In-SystemProgrammingProgrammingdevi